An MPEG RVC AVC Baseline Encoder Based on a Novel Iterative Methodology

With the emergence of new generations of multicore architectures, the need for efficient multimedia algorithm implementations has become critical. This paper describes a new methodology for efficient implementations of algorithms targeting reconfigurable architectures. The Reconfigurable Video Coding (RVC) standard aims to provide a framework allowing a dynamic development,implementation and adoption of standardized video coding solutions with features of higher flexibility and reusability. RVC-CAL actor language is a dataflow language that makes better use of the multicore and parallel architectures. The proposed design flow methodology follows an iteration-based implementation model rather than the traditional sequential model. Analysis, design, development, simulation, testing and adaptation are performed with every iteration ending up with a functional “version” of the algorithm. A case study is conducted to illustrate the productivity of the proposed methodology in which the implementation of an AVC baseline encoder on a Xilinx Virtex 5 XC5VLX50T FPGA demonstrated for intra prediction architecture search space co-exploration.