NetCilk: Extending Task-Level Parallelism Seamlessly across FPGAs

Task-level parallelism (TLP) is a long-standing approach in parallelizing control-dominated algorithms in software and has recently drawn interest in hardware acceleration thanks to the simplicity of managing tasks in hardware. Several TLP frameworks for FPGAs, like ParallelXL and HardCilk, leverage high-level synthesis to facilitate the acceleration of efficient TLP algorithms on FPGAs. In particular, HardCilk managed to efficiently deploy up to 256 processing elements (PEs) on a single FPGA system for microbenchmarks. However, for practical applications, it is usually not possible to fit more than a dozen PEs per FPGA, a limitation that reduces the potential of TLP. In this work, we propose an architecture that exploits the latency insensitivity of TLP and the high-bandwidth networking available in modern FPGAs to increase the number of available PEs for a given workload. We show that it is possible to span multiple FPGAs without loss of efficiency and with only a small resource overhead. We conduct experiments that distribute 128 PEs among two, four, and eight FPGAs and compare the efficiency with that of a single FPGA HardCilk system for a representative set of benchmarks. Our results accentuate the importance of an effective task movement policy across FPGAs to achieve scalability, particularly under specific network latency and bandwidth configurations. We also develop three real-world applications and test with two FPGAs setup, achieving almost perfect scalability. Our architecture achieves multi-FPGA extension with less than 3% of additional resource utilization.