How to Measure the Killer Microsecond

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

In-network devices around the world monitor and tamper with connections for many reasons, including intrusion prevention, combating spam or phishing, and country-level censorship. Connection tampering seeks to block access to specific domain names or keywo ...

Time-sensitive networks, as in the context of IEEE Time-Sensitive Networking (TSN) and IETF Deterministic Networking (DetNet), offer deterministic services with guaranteed bounded latency in order to support safety-critical applications. In this thesis, we ...

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

Keeping track of Internet latency is a classic measurement problem. Open measurement platforms like RIPE Atlas are a great solution, but they also face challenges: preventing network overload that may result from uncontrolled active measurements, and maint ...

The crowdedness of the RF spectrum constitutes problems in communication, however it also accommodates large amount of useful information. This information can be used to determine existing signals and operating contexts. However, spectrum condition varies ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

Online services have become ubiquitous in technological society, the global demand for which has driven enterprises to construct gigantic datacenters that run their software. Such facilities have also recently become a substrate for third-party organizatio ...

Decentralized signal control of congested traffic networks based on the Max-Pressure (MP) controller is theoretically proven to maximize throughput, stabilize the system and balance queues for single intersections under specific conditions. However, its pe ...

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

How to Measure the Killer Microsecond

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Highly Parallel RTL Simulation

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Global, Passive Detection of Connection Tampering

Worst-Case Delay Analysis of Time-Sensitive Networks with Network Calculus

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Using Gaming Footage as a Source of Internet Latency Information

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

Chaosity: Understanding Contemporary NUMA-architectures

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

FPGA-to-CPU Undervolting Attacks

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Hardware and Software Support for RPC-Centric Server Architecture

Critical node selection method for efficient Max-Pressure traffic signal control in large-scale congested networks

From C/C plus plus Code to High-Performance Dataflow Circuits