Publications associées à An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

Publications associées (11)

SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Rafael Medina Morillas, Pengbo Yu

By interfacing computing logic directly to the DRAM banks, bank-level Compute-near-Memory (CnM) architectures promise to mitigate the bottleneck at the memory interconnect. While this computation paradigm heavily reduces the energy requirements for data mo ...

ACM2025

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

Micro-architectural Analysis of In-memory OLTP

Anastasia Ailamaki, Pinar Tözün, Danica Porobic, Utku Sirin

Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP mostly under-utilize the available micro-architectural ...

2016

Parallel Inverse Kinematics for Multithreaded Architectures

Pawan Kumar Harish, Ronan Boulic, Benoît Le Callennec, Mentar Mahmudi

In this article, we present a parallel prioritized Jacobian-based inverse kinematics algorithm for multithreaded architectures. We solve damped least squares inverse kinematics using a parallel line search by identifying and sampling critical input paramet ...

Association for Computing Machinery2016

Energy-Efficient Inexact Speculative Adder with High Performance and Accuracy Control

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical ou ...

2015

Applying HTM to an OLTP System: No Free Lunch

Anastasia Ailamaki, Pinar Tözün, Danica Porobic

Transactional memory is a promising way for implementing efficient synchronization mechanisms for multicore processors. Intel's introduction of hardware transactional memory (HTM) into their Haswell line of processors marks an important step toward mainstr ...

2015

ALLARM: Optimizing Sparse Directories for Thread-Local Data

Amitabha Roy

Large-scale cache-coherent systems often impose unnecessary overhead on data that is thread-private for the whole of its lifetime. These include resources devoted to tracking the coherence state of the data, as well as unnecessary coherence messages sent o ...

2014

SHIFT: Shared History Instruction Fetch for Lean-Core Server Processors

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

2013

Multicore thermal management using approximate explicit Model Predictive Control

Giovanni De Micheli, David Atienza Alonso, Colin Neil Jones, Francesco Zanini

Meeting temperature constraints and reducing the hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. In this paper we aim at achieving an online smooth thermal control action that minimizes the performance l ...

IEEE Press2010

Last-touch correlated data streaming

Babak Falsafi, Michael Ferdman

Recent research advocates address-correlating predictors to identify cache block addresses for prefetch. Unfortunately, address-correlating predictors require correlation data storage proportional in size to a program's active memory footprint. As a result ...

2007