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ALLARM: Optimizing Sparse Directories for Thread-Local Data

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The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

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Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

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Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

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Caching and Neutrality

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We are used to defining network neutrality as absence of traffic differentiation, like policing or shaping. These mechanisms, however, are often not what determines end-users’ quality of experience (QoE). Most content today is accessed through edge caches, ...

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Acceleration of graph pattern mining and applications to financial crime

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Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

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2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

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Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

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Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

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Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

ACM2023

One-shot Garbage Collection for In-memory OLTP through Temporality-aware Version Storage

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Most modern in-memory online transaction processing (OLTP) engines rely on multi-version concurrency control (MVCC) to provide data consistency guarantees in the presence of conflicting data accesses. MVCC improves concurrency by generating a new version o ...

ACM2023

Special Session: Challenges and Opportunities for Sustainable Multi-Scale Computing Systems

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Multi-Scale computing systems aim at bringing the computing as close as possible to the data sources, to optimize both computation and networking. These systems are composed of at least three computing layers: the terminal layer, the edge layer, and the cl ...

ACM2023

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2.5D Systems-on-Package (SoPs) are composed by several chiplets placed on an interposer. They are becoming increasingly popular as they enable easy integration of electronic components in the same package and high fabrication yields. Nevertheless, they int ...

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Ognjen Glamocanin, Shashwat Shrivastava

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

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ACTOR: Action-Guided Kernel Fuzzing

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Fuzzing reliably and efficiently finds bugs in software, including operating system kernels. In general, higher code coverage leads to the discovery of more bugs. This is why most existing kernel fuzzers adopt strategies to generate a series of inputs that ...

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SecureCells: A Secure Compartmentalized Architecture

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Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

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Latency Interfaces for Systems Code

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This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

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