A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

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A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

Chattez avec Graph Search

Avant-Garde: Empowering GPUs with Scaled Numeric Formats

Secure Interface Design Leveraging Hardware/Software Support

Highly Parallel RTL Simulation

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Oligolithic Cross-task Optimizations across Isolated Workloads

An interior penalty coupling strategy for isogeometric non-conformal Kirchhoff-Love shell patches

EdgeAI-Aware Design of In-Memory Computing Architectures

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

SecureCells: A Secure Compartmentalized Architecture

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Chaosity: Understanding Contemporary NUMA-architectures

An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing

A modelling framework for modern heritage buildings energy simulation

Measurement of WBG-based power supplies

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs