Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle

This paper presents a new hybrid A/D conversion principle based on the combination of an incremental conversion for the most significant part of the result and on a cyclic conversion for the least significant part. The proposed approach exhibits a resolution comparable to a multiorder sigma–delta A/D converter (ADC), but with a higher conversion rate (typically a factor of two) and/or a lower complexity, at the cost of a more stringent antialiasing filter requirement. After having presented the basic equations of the conversion principle, a theoretical analysis of the resolution limitations is given, based on nonidealities and noise considerations. Finally, a switched-capacitor implementation example is given with the corresponding simulations, consisting of a low-complexity 14-b ADC suited for applications requiring medium-speed and very compact ADC.