Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

Anomaly Detection systems based on Machine and Deep learning are the most promising solutions to detect cyberattacks in the industry. However, these techniques are vulnerable to adversarial attacks that downgrade prediction performance. Several techniques ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Harnessing quantum randomness for the generation of random numbers is an important concept crucial for information security and many other computer-related applications. Quantum random number generators (QRNGs) are evolving from bulky, slow, and expensive ...

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

Emerging applications in new generation electronic devices require effective heat removal and thermal man-agement. In this regard, boiling is a phase change phenomenon capable of dissipating a large amount of heat compared to the sensible heat. In this stu ...

High-level synthesis tools, both commercial and academic, typically rely on static scheduling to produce high-throughput pipelines. However, in applications with unpredictable memory accesses or irregular control flow, these tools need to make pessimistic ...

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

Perception and interpretation of the terrain is essential for robot navigation, particularly in off-road areas, where terrain characteristics can be highly variable. When planning a path, features such as the terrain gradient and roughness should be consid ...

We consider the community detection problem in a sparse q-uniform hypergraph G, assuming that G is generated according to the Hypergraph Stochastic Block Model (HSBM). We prove that a spectral method based on the non-backtracking operator for hypergraphs w ...

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Chattez avec Graph Search

From C/C plus plus Code to High-Performance Dataflow Circuits

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

A Methodology for Evaluating the Robustness of Anomaly Detectors to Adversarial Attacks in Industrial Scenarios

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Random flip-flop: adding quantum randomness to digital circuits for improved cyber security, artificial intelligence and more

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

A parametric study on pool boiling heat transfer and critical heat flux on structured surfaces with artificial cavities

Invited Tutorial Dynamatic: From C/C plus plus to Dynamically Scheduled Circuits

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Inter-actions parallel execution on GPU from high-level dataflow synthesis

How Rough Is the Path? Terrain Traversability Estimation for Local and Global Path Planning

Combining Dynamic & Static Scheduling in High-level Synthesis

Sparse random hypergraphs: Non-backtracking spectra and community detection

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs