Formal Analysis of SystemC Designs in Process Algebra

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Data races have long been a notorious problem in concurrent programming. They are subtle to detect, and lead to non-deterministic behaviours. There has been a lot of interest in type systems that statically guarantee data race freedom. Significant progress ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to ph ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

Formally verifying the correctness of software network functions (NFs) is necessary for network reliability, yet existing techniques require full source code and mandate the use of specific data structures. We describe an automated technique to verify NF b ...

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

Formal verification of real-world software systems remains challenging for a number of reasons, including lack of automation, friction in specifying properties, and limited support for the diverse programming paradigms used in industry. In this thesis we m ...

Model-checking intends to verify whether a property is satisfied by a model, or not. Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present papers proposes a ne ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

Software network functions (NFs), such as a network address translator, load balancer, or proxy, promise to bring flexibility and rapid innovation to computer networks and to reduce operational costs. However, continuous updates and flexibility typically c ...

Program synthesis was first proposed a few decades ago, but in the last decade it has gained increased momentum in the research community. The increasing complexity of software has dictated the urgent need for improved supporting tools that verify the soft ...

The concept of IoT-based Smart Cities has gained momentum in recent years. The research in this domain has focused on modeling key characteristics of future smart cities along with exploring their design and implementation aspects from multiple perspective ...

A distance bounding (DB) protocol is a two-party authentication protocol between a prover and a verifier which is based on the distance between the prover and the verifier. It aims to defeat threats by malicious provers who try to convince that they are cl ...

In this paper we introduce an open source and reproducible microphone array hardware design and an anechoic dataset recorded with this array. The Pyramic array has 48 microphones spread onto six identical modules connected to an FPGA-ARM combo. The arrange ...

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

While type soundness proofs are taught in every graduate PL class, the gap between realistic languages and what is accessible to formal proofs is large. In the case of Scala, it has been shown that its formal model, the Dependent Object Types (DOT) calculu ...

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the ...

Formal Analysis of SystemC Designs in Process Algebra

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Highly Parallel RTL Simulation

Degrees of Separation: A Flexible Type System for Safe Concurrency

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Analytic modelling of passive microfluidic mixers

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Automated Verification of Network Function Binaries

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Scaling Language Features for Program Verification

Direct Model-checking of SysML Models

High-Level Synthesis of Dynamically Scheduled Circuits

Verification of Software Network Functions with No Verification Expertise

Scaling Functional Synthesis and Repair

Formal Analysis of Human-Assisted Smart City Emergency Services

Formal Analysis of Distance Bounding with Secure Hardware

Pyramic: Full Stack Open Microphone Array Architecture And Dataset

System Level simulation framework for the ASICs development of a novel particle physics detector

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Type Soundness Proofs with Definitional Interpreters

Hierarchical Reversible Logic Synthesis Using LUTs

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems