Low-power processor architecture exploration for online biomedical signal analysis

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The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

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Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

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Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

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Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

Low-power processor architecture exploration for online biomedical signal analysis

Chattez avec Graph Search

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Imaging sensor device using an array of single-photon avalanche diode photodetectors

EdgeAI-Aware Design of In-Memory Computing Architectures

Highly Parallel RTL Simulation

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Chaosity: Understanding Contemporary NUMA-architectures

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Imprecise Store Exceptions

Green Cryptography and Other Optimisations

Acceleration of graph pattern mining and applications to financial crime