Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

Diffusion-based generative methods have proven effective in modeling trajectories with offline datasets. However, they often face computational challenges and can falter in generalization, especially in capturing temporal abstractions for long- horizon tas ...

In light of the challenges posed by climate change and the goals of the Paris Agreement, electricity generation is shifting to a more renewable and decentralized pattern, while the operation of systems like buildings is increasingly electrified. This calls ...

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

Dual-channel gate driver is commonly utilized in the industry for accommodating the widespread use of half-bridge power modules. As wide-bandgap devices become increasingly prevalent due to their superior switching characteristics compared with conventiona ...

Conventional techniques for purifying macromolecular conjugates often require complex and costly installments that are inaccessible to most laboratories. In this work, we develop a one-step micropreparative method based on a trilayered polyacrylamide gel e ...

Atomic force microscopy (AFM), a member of the scanning probe microscopy (SPM) family, holds a unique position as a nano-characterization instrument in the fields of physics, chemistry, and biology. Its ability to provide atomic resolution and operate in v ...

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

Control design for robotic systems is complex and often requires solving an optimization to follow a trajectory accurately. Online optimization approaches like Model Predictive Control (MPC) have been shown to achieve great tracking performance, but requir ...

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

Exploring a wide range of design options is crucial for every sound conceptual design process. In the conventional structural design workflow, optimization techniques are generally employed to generate well-performing design options. However, focusing only ...

This paper presents a theoretical analysis of linear interpolation as a principled method for stabilizing (large-scale) neural network training. We argue that instabilities in the optimization process are often caused by the nonmonotonicity of the loss lan ...

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Recently, we published an article [1] presenting how the Power Electronics course at the bachelor level is organized by the Power Electronics Laboratory and taught at Ecole Polytechnique Fédérale de Lausanne, EPFL, Switzerland. For those avid readers who m ...

The finite element method is a well-established method for the numerical solution of partial differential equations (PDEs), both linear and nonlinear. However, the repeated re -assemblage of finite element matrices for nonlinear PDEs is frequently pointed ...

Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Chattez avec Graph Search

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Highly Parallel RTL Simulation

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

EdgeAI-Aware Design of In-Memory Computing Architectures

SIMPLE HIERARCHICAL PLANNING WITH DIFFUSION

Quantifying the Unknown: Data-Driven Approaches and Applications in Energy Systems

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

A Dual-Channel Gate Driver Design with Active Voltage Balancing Circuit for Series Connection of SiC MOSFETs

Micropreparative Gel Electrophoresis for Purification of Nanoscale Bioconjugates

Advancing atomic force microscopy through open source instrumentation

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Training Efficient Controllers via Analytic Policy Gradient

A Visionary Look at the Security of Reconfigurable Cloud Computing

Computational conceptual design — typological exploration of spatial truss systems through optimization

Stable Nonconvex-Nonconcave Training via Linear Interpolation

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Learning With Your PETS

On the fast assemblage of finite element matrices with application to nonlinear heat transfer problems