Publications associées à Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Mirjana Stojilovic, Wei Hu, Dina Gamaleldin Ahmed Shawky Mahmoud, Beatrice Shokry Samir Shokry

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

SIMPLE HIERARCHICAL PLANNING WITH DIFFUSION

Chang Chen, Caglar Gulcehre

Diffusion-based generative methods have proven effective in modeling trajectories with offline datasets. However, they often face computational challenges and can falter in generalization, especially in capturing temporal abstractions for long- horizon tas ...

2024

Quantifying the Unknown: Data-Driven Approaches and Applications in Energy Systems

Paul Scharnhorst

In light of the challenges posed by climate change and the goals of the Paris Agreement, electricity generation is shifting to a more renewable and decentralized pattern, while the operation of systems like buildings is increasingly electrified. This calls ...

EPFL2024

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

Ruben Rodriguez, David Atienza Alonso, Benoît Walter Denkinger, Giovanni Ansaloni, José Angel Miranda Calero, Juan Pablo Sapriza Araujo, Rubén Rodríguez Álvarez

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

2024

A Dual-Channel Gate Driver Design with Active Voltage Balancing Circuit for Series Connection of SiC MOSFETs

Drazen Dujic

Dual-channel gate driver is commonly utilized in the industry for accommodating the widespread use of half-bridge power modules. As wide-bandgap devices become increasingly prevalent due to their superior switching characteristics compared with conventiona ...

2024

Micropreparative Gel Electrophoresis for Purification of Nanoscale Bioconjugates

Vitalijs Zubkovs, Ardemis Anoush Boghossian, Sayyed Hashem Sajjadi, Shang-Jung Wu, Yahya Rabbani

Conventional techniques for purifying macromolecular conjugates often require complex and costly installments that are inaccessible to most laboratories. In this work, we develop a one-step micropreparative method based on a trilayered polyacrylamide gel e ...

2024

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

Training Efficient Controllers via Analytic Policy Gradient

Dario Floreano, Davide Scaramuzza, Valentin Wüest

Control design for robotic systems is complex and often requires solving an optimization to follow a trajectory accurately. Online optimization approaches like Model Predictive Control (MPC) have been shown to achieve great tracking performance, but requir ...

New York2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Computational conceptual design — typological exploration of spatial truss systems through optimization

Corentin Jean Dominique Fivet, Jonas Warmuth, Pierluigi D'Acunto

Exploring a wide range of design options is crucial for every sound conceptual design process. In the conventional structural design workflow, optimization techniques are generally employed to generate well-performing design options. However, focusing only ...

International Association for Shell and Spatial Structures (IASS)2023

Stable Nonconvex-Nonconcave Training via Linear Interpolation

Volkan Cevher, Thomas Michaelsen Pethick, Wanyun Xie

This paper presents a theoretical analysis of linear interpolation as a principled method for stabilizing (large-scale) neural network training. We argue that instabilities in the optimization process are often caused by the nonmonotonicity of the loss lan ...

2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Ognjen Glamocanin, Dina Gamaleldin Ahmed Shawky Mahmoud

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

Learning With Your PETS

Drazen Dujic, Max Dupont, Jules Christian Georges Macé, Renan Pillon Barcelos, Andrea Cervone

Recently, we published an article [1] presenting how the Power Electronics course at the bachelor level is organized by the Power Electronics Laboratory and taught at Ecole Polytechnique Fédérale de Lausanne, EPFL, Switzerland. For those avid readers who m ...

2023

On the fast assemblage of finite element matrices with application to nonlinear heat transfer problems

Yannis Dirk Voet

The finite element method is a well-established method for the numerical solution of partial differential equations (PDEs), both linear and nonlinear. However, the repeated re -assemblage of finite element matrices for nonlinear PDEs is frequently pointed ...

ELSEVIER SCIENCE INC2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023