Logic Synthesis and Optimization for CMOS and Post-CMOS Technologies

Logic synthesis is a cornerstone of electronic design automation (EDA), facilitating the optimization of power, performance, and area (PPA) in integrated circuits. As complementary metal-oxide-semiconductor (CMOS) technology approaches its physical limitations, achieving further improvements using conventional methods has become increasingly difficult. Simultaneously, emerging post-CMOS technologies offer significant potential for enhanced energy efficiency, performance, and scalability, but introduce unique constraints that are often unmet by traditional synthesis approaches. Motivated by these challenges, this thesis explores two key research directions: advanced optimization techniques for CMOS and novel synthesis methodologies tailored to post-CMOS technologies.

The first part of this thesis focuses on advancing CMOS logic synthesis through sequential optimization, which exploits the broader solution space afforded by the reachable states of memory elements. We introduce a scalable algorithm leveraging sequential observability don't cares (SODCs) to enhance redundancy removal and resubstitution via k-step sequential induction. Our approach achieves an average area reduction of 6.9% after technology mapping, with post-layout reductions of 2.89% and 1.43% in combinational and sequential areas, respectively.

The second part of this thesis addresses the specific constraints of emerging post-CMOS technologies, including fanout limits, path balancing, and planarization requirements. First, we treat fanout-bounded synthesis as a general problem, considering its applications also in the CMOS domain; we develop exact and heuristic algorithms for fanout-bounded synthesis, realizing an average area reduction of 11.82% compared to state-of-the-art (SOTA) techniques. We also demonstrate the adaptability of these methods to emerging technologies such as adiabatic quantum-flux-parametron (AQFP) circuits. We then propose an exact-synthesis-database-driven approach for solving the splitter and buffer insertion problem in superconducting electronics, achieving up to 40% reduction in critical path delay and a 21% decrease in area for AQFP circuits. Finally, building on the same database-driven approach, we present a general synthesis framework for emerging technologies, incorporating planarization constraints that are particularly critical for field-coupled nanocomputing (FCN) technologies. For FCN technology, our method reduces buffer count, crossing count, and critical path length by 84.5%, 74.5%, and 65.2%, respectively.

This thesis provides scalable and effective methodologies for optimizing circuits in both CMOS and post-CMOS domains. By advancing sequential synthesis and integrating emerging technology constraints into the synthesis process, this work establishes a foundation for the efficient design of next-generation digital systems.