Majority Logic Synthesis

À propos
Confidentialité
Mentions légales

Graph Chatbot

Publications associées (32)

Page 2 sur 2

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Revisiting the Impact of Morphology and Oxidation State of Cu on CO2 Reduction Using Electrochemical Flow Cell

Michael Graetzel, Shaik Mohammed Zakeeruddin, Dan Ren, Jing Gao

Electroreduction of carbon dioxide (CO2) in a flow electrolyzer represents a promising carbon-neutral technology with efficient production of valuable chemicals. In this work, the catalytic performance of polycrystalline copper (Cu), Cu2O-derived copper (O ...

AMER CHEMICAL SOC2022

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Francesco Regazzoni, Andrea Guerrieri, Andres Upegui

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Ayatallah Ahmed Gamal Kamal Elakhras

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

IEEE COMPUTER SOC2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programmi ...

2022

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Alexandre Schmid

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

IEEE2022

H I constraints from the cross-correlation of eBOSS galaxies and Green Bank Telescope intensity maps

Jean-Paul Richard Kneib

We present the joint analysis of Neutral Hydrogen (H I) Intensity Mapping observations with three galaxy samples: the Luminous Red Galaxy (LRG) and Emission Line Galaxy (ELG) samples from the eBOSS survey, and the WiggleZ Dark Energy Survey sample. The H I ...

OXFORD UNIV PRESS2022

Gravitational wave signal from primordial magnetic fields in the Pulsar Timing Array frequency band

Andrii Neronov

The NANOGrav, Parkes, European, and International Pulsar Timing Array (PTA) Collaborations have reported evidence for a common-spectrum process that can potentially correspond to a stochastic gravitational wave background (SGWB) in the 1-100 nHz frequency ...

American Physical Society2022

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

IEEE2021

Symmetry in design and decoding of polar-like codes

Kirill Ivanov

The beginning of 21st century provided us with many answers about how to reach the channel capacity. Polarization and spatial coupling are two techniques for achieving the capacity of binary memoryless symmetric channels under low-complexity decoding algor ...

EPFL2022