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Finding a Needle in the Haystack of Hardened Interconnect Patterns

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Publications associées (34)

Page 2 sur 2

A New Basic Logic Structure for Data-Path Computation

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

2014

Endurance Management for Resistive Logic-In-Memory Computing Architectures

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken

Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low writ ...

Ieee2017

A Circuit Synthesis Flow for Controllable-Polarity Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Double-Gate (DG) controllable-polarity Field-Effect Transistors (FETs) are devices whose n- or p- polarity is on-line configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotuges a ...

Institute of Electrical and Electronics Engineers2014

A general purpose FPGA-based real-time simulator for power systems applications

Farhad Rachidi-Haeri, Mario Paolone, Reza Razzaghi

This paper presents an FPGA-based (field programmable gate array) real-time digital simulator for power systems and power electronics applications. The proposed approach integrates the Modified Nodal Analysis (MNA) method, the Fixed Admittance Matrix Nodal ...

IEEE Power Engineering Society2013

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

IEEE/ACM Press2013

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

Christos Kozyrakis

Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby ...

Ieee2016

Fast Simulation of Electromagnetic Transients in Power Systems : Numerical Solvers and their Coupling with the Electromagnetic Time Reversal Process

Reza Razzaghi

The development of modern and future power systems is associated with the definition of new approaches for their simulation, control, and protection. To give an example, the increasing connection of massive renewable energy conversion systems is justifying ...

EPFL2016

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Paolo Ienne, Madhura Purnaprajna

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimising this performance gap by using fixed, fine-grained, non-programmable logic structures in place o ...

Ieee2013

The Programmable Logic-in-Memory (PLiM) Computer (Invited)

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits ...

Ieee2016

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Christos Kozyrakis

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devi ...

Ieee2016

Closing the Gap between FPGA and ASIC : Balancing Flexibility and Efficiency

Hadi Parandeh Afshar

Despite many advantages of Field-Programmable Gate Arrays (FPGAs), they fail to take over the IC design market from Application-Specific Integrated Circuits (ASICs) for high-volume and even medium-volume applications, as FPGAs come with significant cost in ...

EPFL2012

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Xifan Tang, Gain Kim

Nowadays, Field Programmable Gate Arrays (FPGA) exploit Look-Up Tables (LUTs) to generate logic functions. A K-input LUT can implement any Boolean functions with K inputs. Thanks to this flexibility, LUTs remained concep ...

2015

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015