DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

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Determining an optimum quantity of interleaved instruction streams of defined coroutines

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include performing a first database operation by at least executing a first instruction stream associated with the first database operation. The first database opera ...

2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Latency Interfaces for Systems Code

Rishabh Ramesh Iyer

This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

EPFL2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Overflow-free compute memories for edge AI acceleration

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

Compute memories are memory arrays augmented with dedicated logic to support arithmetic. They support the efficient execution of data-centric computing patterns, such as those characterizing Artificial Intelligence (AI) algorithms. These architectures can ...

2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Efficient Concurrent Analytical Query Processing using Data and Workload-conscious Sharing

Panagiotis Sioulas

Analytical workloads are evolving as the number of users surges and applications that submit queries in batches become popular. However, traditional analytical databases that optimize-then-execute each query individually struggle to provide timely response ...

EPFL2023

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

2023

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

Mathias Josef Payer, Flavio Toffalini, Luca Di Bartolomeo

Code-reuse attacks are dangerous threats that attracted the attention of the security community for years. These attacks aim at corrupting important control-flow transfers for taking control of a process without injecting code. Nowadays, the combinations o ...

IEEE COMPUTER SOC2023

Silent Bugs Matter: A Study of Compiler-Introduced Security Bugs

Mathias Josef Payer

Compilers assure that any produced optimized code is semantically equivalent to the original code. However, even "correct" compilers may introduce security bugs as security properties go beyond translation correctness. Security bugs introduced by such corr ...

Usenix Assoc2023