AIPS: AI-Based Power Simulation for Pre-silicon Side-Channel Security Evaluation

This directory contains the design files corresponding to the paper "AIPS: AI-Based Power Simulation for Pre-silicon Side-Channel Security Evaluation "(https://doi.org/10.5281/zenodo.18158825) by Ya Gao, Haocheng Ma, Tanchen Zhang, Jiaji He, Yiqiang Zhao, Mirjana Stojilovic, Yier Jin.

The README file details the repository's structure, contents, and instructions for using the provided data.

Abstract:

Power side-channel analysis (SCA) attacks pose a significant threat to the security of integrated circuits, making pre-silicon evaluation essential for vulnerability identification. Existing solutions face a fundamental trade-off. Commercial electronic design automation (EDA) tools produce accurate transient power traces but are prohibitively slow as design size and trace length grow, while recent AI methods target average power for design purposes and overlook fine-grained transients crucial to SCA.

To address these challenges, we propose AIPS, a AI-based Power Simulation framework at gate-level. AIPS includes parsers to efficiently extract switching activity and technology information, and a diffusion model that reconstructs these features into accurate transient power traces. AIPS is trained using power traces generated by Synopsys PrimeTime PX (PTPX) and is evaluated on 5 representative circuits (AES, Kyber, two masked AES variants and RISC-V) through first- and higher-order SCAs on AIPS-predicted traces. Results show that AIPS matches PTPX-level accuracy while achieving significant efficiency gains (up to 10,000x) in pure inference mode. High accuracy is maintained even with small training sets (~500 traces), and efficiency scales well with increasing trace length, highlighting AIPS as a scalable and practical tool for fast pre-silicon side-channel security evaluation.