Publications associées à Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches

Luca Di Bartolomeo, Mathias Josef Payer, Flavio Toffalini, Jianhao Xu

Code-reuse attacks are dangerous threats that attracted the attention of the security community for years. These attacks aim at corrupting important control-flow transfers for taking control of a process without injecting code. Nowadays, the combinations o ...

IEEE COMPUTER SOC2023

Silent Bugs Matter: A Study of Compiler-Introduced Security Bugs

Mathias Josef Payer, Jianhao Xu

Compilers assure that any produced optimized code is semantically equivalent to the original code. However, even "correct" compilers may introduce security bugs as security properties go beyond translation correctness. Security bugs introduced by such corr ...

Usenix Assoc2023

MOD2IR: High-Performance Code Generation for a Biophysically Detailed Neuronal Simulation DSL

Felix Schürmann, Pramod Shivaji Kumbhar, Snehal Pramod Kumbhar, Omar Awile, Ioannis Magkanaris

Advances in computational capabilities and large volumes of experimental data have established computer simulations of brain tissue models as an important pillar in modern neuroscience. Alongside, a variety of domain specific languages (DSLs) have been dev ...

ACM2023

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Dr.Jit: A Just-In-Time Compiler for Differentiable Rendering

Sébastien Nicolas Speierer, Nicolas Julien Roussel, Wenzel Alban Jakob, Delio Aleardo Vicini

Dr.Jit is a new just-in-time compiler for physically based rendering and its derivative. Dr.Jit expedites research on these topics in two ways: first, it traces high-level simulation code (e.g., written in Python) and aggressively simplifies and specialize ...

2022

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Faster Parallel Training of Word Embeddings

Martin Jaggi

Word embeddings have gained increasing popularity in the recent years due to the Word2vec library and its extension fastText that uses subword information. In this paper, we aim at improving the execution speed of fastText training on homogeneous multi- an ...

IEEE COMPUTER SOC2021

Micro-architectural Analysis of Database Workloads

Utku Sirin

Database workloads have significantly evolved in the past twenty years. Traditional database systems that are mainly used to serve Online Transactional Processing (OLTP) workloads evolved into specialized database systems that are optimized for particular ...

EPFL2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Just-in-time performance without warm-up

Denys Shabalin

Scala has been developed as a language that deeply integrates with the Java ecosystem. It offers seamless interoperability with existing Java libraries. Since the Scala compiler targets Java bytecode, Scala programs have access to high-performance runtimes ...

EPFL2020

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Anatoly Prihozhy, Endri Bezati, Simone Casale Brunet

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

Semantics-preserving inlining for metaprogramming

Martin Odersky, Nicolas Alexander Stucki, Sébastien Jean R Doeraene

Inlining is used in many different ways in programming languages: some languages use it as a compiler-directive solely for optimization, some use it as a metaprogramming feature, and others lay their design in-between. This paper presents inlining through ...

2020

Combining Dynamic & Static Scheduling in High-level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

ASSOC COMPUTING MACHINERY2020

RetroWrite: Statically Instrumenting COTS Binaries for Fuzzing and Sanitization

Mathias Josef Payer, Duo Xu

Analyzing the security of closed source binaries is currently impractical for end-users, or even developers who rely on third-party libraries. Such analysis relies on automatic vulnerability discovery techniques, most notably fuzzing with sanitizers enable ...

IEEE COMPUTER SOC2020

A review of CUDA optimization techniques and tools for structured grid computing

Mohammad Khaja Nazeeruddin

Recent advances in GPUs opened a new opportunity in harnessing their computing power for general purpose computing. CUDA, an extension to C programming, is developed for programming NVIDIA GPUs. However, efficiently programming GPUs using CUDA is very tedi ...

2020

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

Compiler Generation for Performance-Oriented Embedded DSLs (Short Paper)

Vojin Jovanovic, Christoph Koch, Amir Shaikhha

In this paper, we present a framework for generating optimizing compilers for performance-oriented embedded DSLs (EDSLs). This framework provides facilities to automatically generate the boilerplate code required for building DSL compilers on top of the ex ...

ASSOC COMPUTING MACHINERY2019

Topological Analog Signal Processing

Romain Christophe Rémy Fleury, Farzad Zangeneh Nejad

Analog signal processors have attracted a tremendous amount of attention recently, as they potentially offer much faster operation and lower power consumption than their digital versions. Yet, they are not preferable for large scale applications due to the ...

Nature Research2019