DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

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DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Chattez avec Graph Search

EdgeAI-Aware Design of In-Memory Computing Architectures

Highly Parallel RTL Simulation

Is the powersave governor really saving power?

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Oligolithic Cross-task Optimizations across Isolated Workloads

Integrated Wireless Power, Data Communication, and Thermal Sensing System for Autonomous Multisite Brain Implants

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Chaosity: Understanding Contemporary NUMA-architectures

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Green Cryptography and Other Optimisations

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Imprecise Store Exceptions

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

A Visionary Look at the Security of Reconfigurable Cloud Computing

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles