Publications associées à Formal Verification for Secure Processors: A Guide for Computer Architects

Publications associées (14)

Electrical-Level Fault-Injection Attacks on FPGA-Based Systems

With the growth in the performance of general-purpose computing no longer following Moore's law and Dennard scaling, the use of hardware-specialized systems is common practice. Field-programmable gate arrays (FPGAs) are adopted in cloud and cyber-physical ...

EPFL2024

The JPEG AI Standard: Providing Efficient Human and Machine Visual Data Consumption

Touradj Ebrahimi

The Joint Photographic Experts Group (JPEG) AI learning-based image coding system is an ongoing joint standardization effort between International Organization for Standardization (ISO), International Electrotechnical Commission (IEC), and International Te ...

IEEE COMPUTER SOC2023

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

Modernizing the NEURON Simulator for Sustainability, Portability, and Performance

Nicolas Pierre Jean Cornu, Alexandru Savulescu, Oliver James Lupton, Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Fernando Joaquim Leite Pereira, Omar Awile, Ioannis Magkanaris

The need for reproducible, credible, multiscale biological modeling has led to the development of standardized simulation platforms, such as the widely-used NEURON environment for computational neuroscience. Developing and maintaining NEURON over several d ...

2022

tweedledum: A Compiler Companion for Quantum Computing

Giovanni De Micheli, Bruno Schmitt Antunes

This work presents tweedledum-an extensible open-source library aiming at narrowing the gap between high-level algorithms and physical devices by enhancing the expressive power of existing frameworks. For example, it allows designers to insert classical lo ...

IEEE2022

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Giovanni Ansaloni

Approximate logic synthesis techniques have become popular in error-resilient systems, where accuracy requirements can be traded for improved energy efficiency. Many of these techniques operate on a circuit by substituting or removing some of its portions ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

Paolo Ienne, Stefan Nikolic

Automated switch-block exploration gains in importance as technology scaling brings more emphasis on the physical constraints, making it insufficient to rely on abstract measures of routability alone. In this work, we take an approach that significantly di ...

IEEE COMPUTER SOC2021

Generating hardware and software for RISC-V cores generated with Rocket Chip generator

Endri Bezati

This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow desc ...

IEEE2021

The Cost of Scaling a Reliable Interconnection Topology

Rachid Guerraoui, Alexandre David Olivier Maurer

In distributed computing, many papers try to evaluate the message complexity of a distributed system as a function of the number of nodes n. But what about the cost of building the distributed system itself? Assuming that we want to reliably connect n node ...

2020

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Andreas Peter Burg, Robert Giterman, Adam Shmuel Teman

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations und ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

LUT-Based Hierarchical Reversible Logic Synthesis

Giovanni De Micheli, Mathias Soeken

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUT ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Computational characteristics and hardware implications of brain tissue simulations

Francesco Cremonesi

Understanding the link between the brain's anatomy and its function through computer simulations of neural tissue models is a widely used approach in computational neuroscience. This technique enables rapid prototyping and testing of hypotheses, allowing r ...

EPFL2019

The Mondrian Data Engine

Babak Falsafi, Boris Robert Grot, Javier Picorel Obando, Alexandros Daglis, Mario Paulo Drumond Lages De Oliveira, Dmitrii Ustiugov, Nooshin Sadat Mirzadeh

The increasing demand for extracting value out of ever-growing data poses an ongoing challenge to system designers, a task only made trickier by the end of Dennard scaling. As the performance density of traditional CPU-centric architectures stagnates, adva ...

2017