Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware

In the past decade, computing systems have significantly increased in complexity and power consumption. Nowadays, heterogeneous multi-processor systems-on-chip (MPSoCs) integrate many computing cores. Heterogeneous MPSoCs often comprise general-purpose processors and a variety of accelerators, thus supporting specialized functions for the target application domain to minimize overall energy when executing a specific task. The ensuing architectural design space is, therefore, increasingly multi-dimensional, especially in the light of upcoming 2.5D/3D chiplets integration, which, on one side, allows unprecedented system integration possibilities but, on the other, exacerbates data transfer bottlenecks and affects overall power consumption significantly. To traverse such space in search of high-performance/high-efficiency solutions, we introduce a cross-layer approach combining fast explorations with virtual systems with modular open-hardware design frameworks. This paper showcases how these two approaches effectively cross-fertilize: detailed hardware designs are essential in calibrating performance, power and temperature models, and validating simulation outcomes. Conversely, full system simulation is crucial for projecting the impact of design choices towards complex but energy-efficient heterogeneous multi-processor architectures.