An Efficient Manipulation Package for Biconditional Binary Decision Diagrams

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Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

With the increasing capabilities of the microelectronics technology, future particle detectors in high energy physics will be able to yield high-level features that are not only simple geometrical positions or energy measurement in the silicon sensors used ...

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

Logic synthesis is a key component of digital design and modern EDA tools; it is thus an essential instrument for the design of leading-edge chips and to push the limits of their performance. In the last decades, the electronic circuits community has evolv ...

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...

The study of the complexity of Boolean functions has recently found applications in logic synthesis and optimization algorithms, as for instance in logic rewriting. Previous works have focused on the minimum length of Boolean chains for functions up to 5 i ...

The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

Logic synthesis is an important part of electronic design automation (EDA) flows, which enable the implementation of digital systems. As the design size and complexity increase, the data structures and algorithms for logic synthesis must adapt and improve ...

In-memory computing devices, such as resistive RAMs, natively implement material implication or a variant of the majority-of-three operation called RM3. This operation generalizes material implication and has been used as target operation in sev ...

Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the output(s). The exact ...

An Efficient Manipulation Package for Biconditional Binary Decision Diagrams

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Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Improving Standard-Cell Design Flow using Factored Form Optimization

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

LUT-Based Optimization For ASIC Design Flow

High-Level Synthesis of Dynamically Scheduled Circuits

Three-Input Gates for Logic Synthesis

Development of a Data Concentrator ASIC for the High Luminosity upgrade of the CMS Outer Tracker detector with tracking trigger

Extending Boolean Methods for Scalable Logic Synthesis

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

SAT-Based Exact Synthesis for Multi-Level Logic Networks

The Complexity of Self-Dual Monotone 7-Input Functions

Majority Logic Synthesis

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Exploiting Satisfiability Solvers for Efficient Logic Synthesis

RM3 based logic synthesis

Enabling exact delay synthesis