Publications associées à Arithmetic Optimization for Custom Instruction Set Synthesis

Publications associées (32)

LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Irem Boybat Kara, Flavio Ponzina, Joshua Alexander Harrison Klein, Yuxuan Wang, Abu Sebastian

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing ...

Institute of Electrical and Electronics Engineers (IEEE)2025

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Scalable Logic Rewriting Using Don’t Cares

Giovanni De Micheli, Alessandro Tempia Calvino

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

2024

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

A method and system for optimizing design, implantation, and stimulation protocols of electrodes stimulating the nervous system

Silvestro Micera, Simone Romeni

A method for optimizing at least one of a geometry, an implantation procedure, and/or stimulation protocol of one or more electrodes for an electrical stimulation of a target structure in a nervous system of a living being by a computer device, the method ...

2024

Mesh-based topology, shape and sizing optimization of ribbed plates

Ahmad Abdulrahman Ahmad Majdouba

In this paper, we present a new parameterization and optimization procedure for minimizing the weight of ribbed plates. The primary goal is to reduce embodied CO2 in concrete floors as part of the effort to diminish the carbon footprint of the construction ...

Springer2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Robot Learning using Tensor Networks

Suhan Narayana Shetty

In various robotics applications, the selection of function approximation methods greatly influences the feasibility and computational efficiency of algorithms. Tensor Networks (TNs), also referred to as tensor decomposition techniques, present a versatile ...

EPFL2024

Optimization Algorithms for Decentralized, Distributed and Collaborative Machine Learning

Anastasiia Koloskova

Distributed learning is the key for enabling training of modern large-scale machine learning models, through parallelising the learning process. Collaborative learning is essential for learning from privacy-sensitive data that is distributed across various ...

EPFL2024

Scalable constrained optimization

Maria-Luiza Vladarean

Modern optimization is tasked with handling applications of increasingly large scale, chiefly due to the massive amounts of widely available data and the ever-growing reach of Machine Learning. Consequently, this area of research is under steady pressure t ...

EPFL2024

Highly Parallel RTL Simulation

Seyedmahyar Emami

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

SOMOphilic alkyne vs radical-polar crossover approaches: The full story of the azido-alkynylation of alkenes

Jérôme Waser, Julien Aymeric Borrel

We report the detailed background for the discovery and development of the synthesis of homopropargylic azides by the azidoalkynylation of alkenes. Initially, a strategy involving SOMOphilic alkynes was adopted, but only resulted in a 29% yield of the desi ...

Beilstein-Institut2024

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Technology Mapping Using Multi-output Library Cells

Giovanni De Micheli, Alessandro Tempia Calvino

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

2023

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Matteo Cucchi

Organic electrochemical transistors (OECTs) have gained enormous attention due to their potential for bioelectronics and neuromorphic computing. However, their implementation into real-world applications is still impeded by a lack of understanding of the c ...

WILEY-V C H VERLAG GMBH2023

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

David Spielmann, Mirjana Stojilovic, Ognjen Glamocanin

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

2023

A combined genetic algorithm and active learning approach to build and test surrogate models in Process Systems Engineering

François Maréchal, Julia Granacher

In Process Systems Engineering, computationally-demanding models are frequent and plentiful. Handling such complexity in an optimization framework in a fast and reliable way is essential, not only for generating meaningful solutions but also for providing ...

Pergamon-Elsevier Science Ltd2023

Regularity Matters: Designing Practical FPGA Switch-Blocks

Paolo Ienne, Stefan Nikolic

Several techniques have been proposed for automatically searching for FPGA switch-blocks which typically show some tangible advantage over the well-known academic architectures. However, the resulting switch-blocks usually exhibit high levels of irregulari ...

Assoc Computing Machinery2023