Publications associées à A circuit-level substrate current model for smart-power ICs

Publications associées (33)

Advanced analysis of fully-printed organic transistors platform for multi-ion detection in sweat

Danick Briand, Silvia Demuru, Jaemin Kim, Xi Chen, Brince Paul Kunnel

Organic electrochemical transistors are emerging as prominent biochemical sensors for multi-sensing, including ions, metabolites, hormones, or viruses. However, the implementation of the devices is mainly limited to a single-analyte detection and a single- ...

Elsevier BV2025

Silicon CMOS and InGaAs(P)/InP SPADs for NIR/SWIR detection

Utku Karaca

Applications demanding imaging at low-light conditions at near-infrared (NIR) and short-wave infrared (SWIR) wavelengths, such as quantum information science, biophotonics, space imaging, and light detection and ranging (LiDAR), have accelerated the develo ...

EPFL2024

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

Advanced Silicon and SWIR Single-Photon Avalanche Diodes: Design, Simulation, and Characterization

Ekin Kizilkan

Low-level light detection with high spatial and timing accuracy is a growing area of interest by virtue of applications such as light detection and ranging (LiDAR), biomedical imaging, time-resolved Raman spectroscopy, and quantum applications. Single-phot ...

EPFL2024

SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

Edoardo Charbon, Claudio Bruschini, Francesco Gramuglia, Myung Jae Lee, Ekin Kizilkan, Pouyan Keshavarzian, Won Yong Ha

We present a single-photon avalanche diode (SPAD) developed in 55 nm bipolar-CMOS-DMOS (BCD) technology, which achieves high photon detection probability (PDP) while its breakdown voltage is lower than 20 V. To enhance the PDP performance, the SPAD junctio ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Polarization-enhanced GaN Schottky barrier diodes: Ultra-thin InGaN for high breakdown voltage and low Ron

Elison de Nazareth Matioli, Alessandro Floriduz, Zheng Hao

In this work, we present a concept that leverages the strong piezoelectric polarization field in InGaN, which counteracts the external electric field at reverse bias. We show that despite the smaller InGaN band-gap and lower critical electric field, its st ...

2024

Graph generative deep learning models with an application to circuit topologies

Igor Krawczuk

Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison. Managing their complexity and facilitating their design drove part of the co-evolution of mode ...

EPFL2024

Emulating Multimemristive Behavior of Silicon Nanowire-Based Biosensors by Using CMOS-Based Implementations

Kapil Bhardwaj, Sandro Carrara, Junrui Chen

The research presented in this article draws inspiration from previous efforts aimed at replicating the functions of various solid-state memristors using a variety of materials. The memristor circuit emulator serves as a cost-effective tool for circuit des ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Font Side Solutions for c-Si Solar Cells with High-Temperature Passivating Contacts

Ezgi Genç

In this work, we studied the potential of using thin films deposited by plasma-enhanced chemical vapor deposition (PECVD) for two main purposes: introducing an n-type passivating contact at the front of a TOPCon solar cell, or simplifying the fabrication o ...

EPFL2024

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Zhenyu Wang

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

Plasmonically enhanced molecular junctions for investigation of atomic-scale fluctuations in self-assembled monolayers

Sakthi Priya Amirtharaj

Molecular junctions represent a fascinating frontier in the realm of nanotechnology and are one of the smallest optoelectronic devices possible, consisting of individual molecules or a group of molecules that serve as the active element sandwiched between ...

EPFL2024

Active Voltage Balancing with Seamless Integration into Dual Gate Driver for Series Connection of SiC MOSFETs

Drazen Dujic, Rui Wang

The versatility of half-bridge configuration of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module contributes to its widespread adoption, highlighting the popularity and significance of its corresponding dual gat ...

2024

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Edoardo Charbon, Claudio Bruschini, Myung Jae Lee, Wenfeng Liu

We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers ...

Ieee-Inst Electrical Electronics Engineers Inc2024

An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation

Kyojin Choo

This article presents a triaxial micro electromechani-cal system (MEMS) capacitive accelerometer using a high-voltage biasing technique to achieve high resolution with ultralow power. The accelerometer system generates a differential pair of high voltages ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Highly Parallel RTL Simulation

Seyedmahyar Emami

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Time-resolved multi-gate ion sensitive field effect transducer and system and method of operating the same

Jean-Michel Sallese, Adil Koukab

A time-resolved multi-gate ion sensitive field effect transducer, including a silicon layer, a P-doped region in the silicon layer and a first electrode in electric connection with the P doped region, a N-doped region in the silicon layer and a second elec ...

2023

High Input Impedance Front-End Amplifier for Noncontact Bio-Potential Recording

Alexandre Schmid

In this paper, a high input impedance front-end amplifier is proposed for non-contact bio-potential recording systems. The proposed structure uses a positive feedback network to deliver a neutralization current back to the input node of the circuit to neut ...

Institute of Electrical and Electronics Engineers Inc.2023

Electronic metadevices for terahertz applications

Elison de Nazareth Matioli, Mohammad Samizadeh Nikooytabalvandani

The evolution of electronics has largely relied on downscaling to meet the continuous needs for faster and highly integrated devices(1). As the channel length is reduced, however, classic electronic devices face fundamental issues that hinder exploiting ma ...

NATURE PORTFOLIO2023

Trapping Layers Prevent Dopant Segregation and Enable Remote Doping of Templated Self-Assembled InGaAs Nanowires

Anna Fontcuberta i Morral, Didem Dede, Nicholas Paul Morgan, Valerio Piazza

Selective area epitaxy is a promising approach to definenanowirenetworks for topological quantum computing. However, it is challengingto concurrently engineer nanowire morphology, for carrier confinement,and precision doping, to tune carrier density. We re ...

AMER CHEMICAL SOC2023