A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

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A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

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Improving Standard-Cell Design Flow using Factored Form Optimization

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

High-Performance CMOS SPAD-Based Sensors for Time-of-Flight PET Applications

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Resource Trade-Offs in Circuits and Systems: from Neurotechnology to Communications

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Cryogenic CMOS Integrated Circuits for Scalable Readout of Silicon Quantum Computers

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors