A power-efficient, current-mode, binary-tree min / max circuit for Kohonen self-organizing feature maps and nonlinear filters

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We consider learning of fundamental properties of communities in large noisy networks, in the prototypical situation where the nodes or users are split into two classes according to a binary property, e.g., according to their opinions or preferences on a t ...

Density, speed and energy efficiency of integrated circuits have been increasing exponentially for the last four decades following Moore's law. However, power and reliability pose several challenges to the future of technology scaling. Approximate computin ...

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

We experimentally demonstrate three-fold wavelength multicasting of a 64-quadrature-amplitude-modulation (QAM), 120-Gbit/s data channel using a microresonator Kerr frequency comb and nonlinear wave mixing. The multicasting is achieved with a data signal an ...

The impact of technological advancement became significant and still has an essential role to play in the diagnosis and treatment of diseases. Nowadays, personalized medicine and therapy are on the rise as a consequence of the developed and cheaper medical ...

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consumin ...

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

An accurate 16-channel seizure detection system-on-chip is presented, which is based on extracting features from the compressed recorded data using multichannel compressive sensing (MCS). MCS is used to reduce the transmission data rate of sparse biologica ...

A power-efficient, current-mode, binary-tree min / max circuit for Kohonen self-organizing feature maps and nonlinear filters

Chattez avec Graph Search

Unsupervised Robust Nonparametric Learning Of Hidden Community Properties

Design of approximate and precision-scalable circuits for embedded multimedia and neural-network processing

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Experimental demonstration of three-fold wavelength multicasting of a 64-QAM 120 Gbit/s data channel using a Kerr frequency comb and nonlinear wave mixing

Wireless Power Transfer and Data Communication for Implantable Autonomous Monitoring and Detection of Epilepsy In Vivo

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Adaptive Receiver Design for High Speed Optical Communication

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

A Sub-μW/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing