Conformal Mapping Based DC Current Model For Double Gate Tunnel FETs

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Conformal Mapping Based DC Current Model For Double Gate Tunnel FETs

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Scaling silicon-based quantum computing using CMOS technology

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Comparison of Wide-band-gap Technologies for Soft-Switching Losses at High Frequencies

Electrochemical and morphological engineering of 2D materials for nanopore sensing

InAs-on-Insulator Fin Nanostructures for Integrated Computation and Sensing Functions

At the end of scaling: 2D materials for computing and sensing applications

High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Output Capacitance Losses in Wide-Band-Gap Transistors: A Small-Signal Modeling Approach

An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction