Lukasiewicz Fuzzy Logic Networks and Their Ultra Low Power Hardware Implementation

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A good knowledge of material properties is a critical aspect for modeling high-temperature superconductor (HTS) devices. However, the electrical resistivity of coated conductors above the critical current is limited. The major challenge in characterizing t ...

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for th ...

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Seve ...

The selection criteria for NIST's Lightweight Crypto Standardization (LWC) have been slowly shifting towards the lightweight efficiency of designs, given that a large number of candidates already establish their security claims on conservative, well-studie ...

Cascode topology which includes a high-voltage GaN and a low-voltage Si transistor is an attractive device concept, which uses the low ON-resistance of GaN while still being compatible with Si gate drivers. It demonstrates the highest threshold voltage amo ...

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method fo ...

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

The article firstly proves that the constant quality factor (Q) contours for passive circuits, while represented on a 2D Smith chart, form circle arcs on a coaxal circle family. Furthermore, these circle arcs represent semi-circles families in the north he ...

In this work, we present the investigation of the combination of p-GaN gate and tri-gate structures to achieve normally-off operation on GaN-on-Si MOSFETs. We have developed and optimized a selective and low-damage p-GaN etching recipe to stop at the AlGaN ...

Lukasiewicz Fuzzy Logic Networks and Their Ultra Low Power Hardware Implementation

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Optimization Method for Extracting Stabilizer Geometry and Properties of REBCO Tapes

Subthermionic negative capacitance ion sensitive field-effect transistor

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Energy Analysis of Lightweight AEAD Circuits

Negative Resistance in Cascode Transistors

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction in Junction FETs

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

3D Smith chart constant quality factor semi-circles contours for positive and negative resistance circuits

Investigation of p-GaN tri-Gate normally-Off GaN Power MOSHEMTs