Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

We conducted a comparative user study of the Infinadeck [1] omnidirectional treadmill native control algorithm alongside an approach based on a state observer control scheme combining a kinematic model with error dynamics that allows users to change their ...

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

The Gm/ID approach has proven to be an efficient technique for the design of low-power analog circuits. Until now it was mostly demonstrated on older CMOS technology nodes. In this paper we will show that the Gm/ID methodology still holds for advanced tech ...

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

EC RF power sources will play a major role in the future operation of large scale tokamaks (ITER, DEMO). A 1MW/170GHz gyrotron is the standard RF power unit considered for ITER. Even though the efficiency of such devices has been significantly increased th ...

The acquisition of survey responses is a crucial component in conducting research aimed at comprehending public opinion. However, survey data collection can be arduous, time-consuming, and expensive, with no assurance of an adequate response rate. In this ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

Sexual harassment is prevalent at all levels of higher education and research and in all disciplines, which means that engineering education is no exception. Following the #MeToo movement, students have started to report cases of abuses publicly in our ins ...

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

Timely insights lead to business growth and scientific breakthroughs but require analytical engines that cope with the ever-increasing data processing needs. Analytical engines relied on rapid CPU improvements, yet the end of Dennard scaling stopped the fr ...

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Chattez avec Graph Search

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

EdgeAI-Aware Design of In-Memory Computing Architectures

Highly Parallel RTL Simulation

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

User study of omnidirectional treadmill control algorithms in VR

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Design of Low-power Analog Circuits in Advanced Technology Nodes using the Gm/ID Approach

Chaosity: Understanding Contemporary NUMA-architectures

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Homogenous power distribution along gyrotron collector walls

Predicting Survey Response with Quotation-based Modeling: A Case Study on Favorability towards the United States

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Acceleration of graph pattern mining and applications to financial crime

Supporting Well-Being: A Digital Intervention Model for Disclosing Sexual Harassment in Higher Education

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Efficient Analytical Query Processing on CPU-GPU Hardware Platforms

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs