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Publications associées (31)

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Philip Brisk, Mirjana Stojilovic

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

USSR: An UltraSound Sparse Regularization framework

Jean-Philippe Thiran, Yves Wiaux, Dimitris Perdios, Adrien Georges Jean Besson, Florian Martinez, Marcel Arditi

Ultrafast ultrasound (US) imaging uses unfocused waves to insonify the whole medium of interest at once, allowing pulse-echo US imaging to achieve very high frame rates, at the cost of a lower image quality. In this paper, we present USSR, an UltraSound Sp ...

Ieee2017

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

David Atienza Alonso, Ruben Braojos Lopez, Soumya Subhra Basu, Giovanni Ansaloni, Loris Gérard Duch

Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Compilation Techniques for Incremental Collection Processing

Daniel Lupei

Many map-reduce frameworks as well as NoSQL systems rely on collection programming as their interface of choice due to its rich semantics along with an easily parallelizable set of primitives. Unfortunately, the potential of collection programming is not ...

EPFL2017

Near-Memory Address Translation

Javier Picorel Obando

Virtual memory (VM) is a crucial abstraction in modern computer systems at any scale, from handheld devices to datacenters. VM provides programmers the illusion of an always sufficiently large and linear memory, making programming easier. Although the core ...

EPFL2017

A Scala Library for Testing Student Assignments on Concurrent Programming

Mikaël Mayer, Ravichandhran Kandhadai Madhavan

We present a lightweight library for testing concurrent Scala programs by systematically exploring multiple interleavings between user-specified operations on shared objects. Our library is targeted at beginners of concurrent programming in Scala, runs on ...

Assoc Computing Machinery2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

Parallel Inverse Kinematics for Multithreaded Architectures

Ronan Boulic, Benoît Le Callennec, Mentar Mahmudi, Pawan Kumar Harish

In this article, we present a parallel prioritized Jacobian-based inverse kinematics algorithm for multithreaded architectures. We solve damped least squares inverse kinematics using a parallel line search by identifying and sampling critical input paramet ...

Association for Computing Machinery2016

Locking Made Easy

Rachid Guerraoui, Vasileios Trigonakis, Jelena Antic, Georgios Chatzopoulos

A priori, locking seems easy: To protect shared data from concurrent accesses, it is sufficient to lock before accessing the data and unlock after. Nevertheless, making locking efficient requires fine-tuning (a) the granularity of locks and (b) the locking ...

ACM Press2016

A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

David Atienza Alonso, Ruben Braojos Lopez, Soumya Subhra Basu, Giovanni Ansaloni, Loris Gérard Duch

This paper introduces a novel computing architecture devoted to the ultra-low power analysis of multiple bio-signals. Its structure comprises several processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable ...

2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

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