Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

In recent years, population aging and the consequent higher incidence of noncommunicable diseases, have increased the need for long-term health monitoring. Moreover, as healthcare cost is projected to grow substantially by 2030 in OECD countries, the deman ...

A new generation of manycore processors is on the rise that offers dozens and more cores on a chip and, in a sense, fuses host processor and accelerator. In this paper we target the efficient training of generalized linear models on these machines. We prop ...

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

Numerical simulation of Pelton turbine hydrodynamics is helpful to identify the energy loss mechanisms in the runner and minimize their effect. However, it is a challenging task that involves handling the unsteady free surface flow and moving boundaries re ...

Current cluster computing frameworks suffer from load imbalance and limited parallelism due to skewed data distributions, processing times, and machine speeds. We observe that the underlying cause for these issues in current systems is that they partition ...

Transaction processing is a mission critical enterprise application that runs on high-end servers. Traditionally, transaction processing systems have been designed for uniform core-to-core communication latencies. In the past decade, with the emergence of ...

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Recent trends have led hardware manufacturers to place multiple processing cores on a single chip, making parallel programming the intended way of taking advantage of the increased processing power. However, bringing concurrency to average programmers is c ...

The constant increase in single core frequency reached a plateau during recent years since the produced heat inside the chip cannot be cooled down by existing technologies anymore. An alternative to harvest more computational power per die is to fabricate ...

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Minimizing buffer sizes of dynamic dataflow implementations without introducing deadlocks or reducing the design performance is in general an important and useful design objective. Indeed, buffer sizes that are too small causing a system to deadlock during ...

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power co ...

The recent proliferation of multi-core processors has moved concurrent programming into mainstream by forcing increasingly more programmers to write parallel code. Using traditional concurrency techniques, such as locking, is notoriously difficult and has ...

This paper focuses on the design of an asynchronous broadcast primitive on the Intel SCC. Our solution is based on OC-Bcast, a state-of-the-art k-ary tree synchronous broadcast algorithm that leverages the parallelism provided by on-chip Remote Memory Acce ...

Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel ...

Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs

Chattez avec Graph Search

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Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

System-level Design of Adaptive Wearable Sensors for Health and Wellness Monitoring

On Linear Learning with Manycore Processors

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

GPU-Accelerated Finite Volume Particle Simulation of Free Jet Deviation by Multi-jet Rotating Pelton Runner

Rock You like a Hurricane: Taming Skew in Large Scale Analytics

High Performance Transaction Processing on Non-Uniform Hardware Topologies

Automatic support for multi-module parallelism from computational patterns

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Inferring Scalability from Program Pseudocode

High-Performance Communication Primitives and Data Structures on Message-Passing Manycores : Broadcast and Map

Data Structures and Algorithms for Data-Parallel Computing in a Managed Runtime

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

On the Performance of Software Transactional Memory

Asynchronous Broadcast on the Intel SCC using Interrupts

High-Performance RMA-Based Broadcast on the Intel SCC