High-Performance Communication Primitives and Data Structures on Message-Passing Manycores : Broadcast and Map

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Recent advances in machine learning have dramatically increased model size and computational requirements, increasingly straining computing system capabilities. This tension is particularly acute for resource-constrained edge scenarios, for which careful h ...

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

Genome-wide chromatin conformation capture assays provide formidable insights into the spatial organization of genomes. However, due to the complexity of the data structure, their integration in multi-omics workflows remains challenging. We present data st ...

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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The desire and ability to place AI-enabled applications on the edge has grown significantly in recent years. However, the compute-, area-, and power-constrained nature of edge devices are stressed by the needs of the AI-enabled applications, due to a gener ...

The invention relates to an Imaging sensor device in a stacked arrangement comprising: - a pixel array tier comprising a plurality of pixel segments each having a plurality of pixels for photon detection each providing a digital pixel output; - a processin ...

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

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Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compare ...

We present starred, a point-spread function (PSF) reconstruction, two-channel deconvolution, and light-curve extraction method designed for high-precision photometric measurements in imaging time series. An improved resolution of the data is targeted rathe ...

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Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

High-Performance Communication Primitives and Data Structures on Message-Passing Manycores : Broadcast and Map

Chattez avec Graph Search

Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Secure Interface Design Leveraging Hardware/Software Support

EdgeAI-Aware Design of In-Memory Computing Architectures

Orchestrating chromosome conformation capture analysis with Bioconductor

Highly Parallel RTL Simulation

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Imaging sensor device using an array of single-photon avalanche diode photodetectors

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Integrated Wireless Power, Data Communication, and Thermal Sensing System for Autonomous Multisite Brain Implants

Swift : a modern highly parallel gravity and smoothed particle hydrodynamics solver for astrophysical and cosmological applications

High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes

Image Deconvolution and Point-spread Function Reconstruction with STARRED: A Wavelet-based Two-channel Method Optimized for Light-curve Extraction

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Chaosity: Understanding Contemporary NUMA-architectures

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms