A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

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Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programmi ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this paper, ...

The development and progress of high-throughput sequencing technologies have transformed the sequencing of DNA from a scientific research challenge to practice. With the release of the latest generation of sequencing machines, the cost of sequencing a whol ...

Over-the-air computation (AirComp) is a disruptive technique for fast wireless data aggregation in Internet of Things (IoT) networks via exploiting the waveform superposition property of multiple-access channels. However, the performance of AirComp is bott ...

This paper presents a quality evaluation study of point cloud codecs that have been recently standardised by the MPEG committee. In particular, a subjective experiment to assess their performance in terms of bitrate against visual quality is designed and r ...

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

Atomic lock-free multi-word compare-and-swap (MCAS) is a powerful tool for designing concurrent algorithms. Yet, its widespread usage has been limited because lock-free implementations of MCAS make heavy use of expensive compare-and-swap (CAS) instructions ...

The study of strong gravitational lenses is a relatively new scientific field in astronomy with many applications in cosmology. Its unique observables allow astronomers to trace dark matter, determine the expansion of the universe and study galaxy evolutio ...

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

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Highly Parallel RTL Simulation

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

High-Level Synthesis of Dynamically Scheduled Circuits

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

An Introduction to MPEG-G: The First Open ISO/IEC Standard for the Compression and Exchange of Genomic Sequencing Data

Over-the-Air Computation via Reconfigurable Intelligent Surface

Quality Evaluation Of Static Point Clouds Encoded Using MPEG Codecs

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Efficient Multi-Word Compare and Swap

Methods for strong gravitational lens detection and analysis using machine learning and high performance computing

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms