Publications associées à Implementation and validation of a dual P- and M- class compliant PMU prototype based on the delayed in-quadrature interpolated DFT

Publications associées (13)

Lattice resonances in plasmonic systems

Different phenomena that occur in a periodic array of plasmonic nanostructures are investigated in terms of periodicity and multipoles. In this presentation, we revisit the resonances that exist in periodic plasmonic systems, Fig. 1. Starting with some bas ...

Institute of Physics2025

The JET upgraded toroidal Alfven Eigenmode Diagnostic System

Ambrogio Fasoli, Duccio Testa, Patrick Blanchard

The Alfven Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET. The new system consists of individual 4 kW amplifiers allowing for increased cu ...

2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

Synchronized Sensing for Wide-Area Situational Awareness of Electrical Grids in Non-Stationary Operating Conditions

Asja Derviskadic

Situational-awareness methods and technologies are crucial elements to ensure power systems reliability and security as they are used by automated decision-making processes of mission-critical applications. Inadequate system monitoring results in incorrect ...

EPFL2019

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Single-FPGA complete 3D and 2D medical ultrasound imager

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Aya Mohamed Naguib Ahmed Ibrahim, Marcel Arditi, Damien Doy

3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machi ...

IEEE2017

Spin waves with large decay length and few 100 nm wavelengths in thin yttrium iron garnet grown at the wafer scale

Dirk Grundler

Using conventional coplanar waveguides (CPWs), we excited spin waves with a wavelength λ down to 310 nm in a 200 nm thin yttrium iron garnet film grown by liquid phase epitaxy. Spin-wave transmission was detected between CPWs that we separated by up to 2 m ...

American Institute of Physics2017

An MIG-based Compiler for Programmable Logic-in-Memory Architectures

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Luca Gaetano Amarù

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on r ...

Ieee2016

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

A Novel FPGA Architecture based on Ultra-Fine Grain Reconfigurable Logic Cells

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Gain Kim

In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n- or p-ty ...

Institute of Electrical and Electronics Engineers2015

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

IEEE/ACM Press2013