Optimizing Data-Center TCO with Scale-Out Processors

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Optimizing Data-Center TCO with Scale-Out Processors

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Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

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Sensitivity to user mischaracterizations in electric vehicle charging

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Systematic benchmarking of single-cell ATAC-sequencing protocols

Hardware-Software co-design Methodologies for Edge AI Optimization

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

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Demand-based operations of vehicle sharing systems

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Modeling and mitigating supply chain disruptions as a bilevel network flow problem

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Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

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