A 78.2/90.0dB-SNDR/SFDR Pipelined-SAR ADC with Noise-Reducing Stacked Dynamic Source-Follower Amplifiers

A pipelined-SAR ADC is a popular front-end solution for highresolution, low-power loT sensors, as it combines the noise relaxation property of residue amplification with the robustness of SAR ADCs, enabling excellent energy efficiency and high-resolution readout. Residue amplifiers (RAs) are the key innovation point for these ADCs, as recent efforts have focused on replacing statically powered RAs with dynamic amplifiers, such as ring amplifiers [1–4], floating inverter amplifiers (FIAs) [5–7], or various open-loop amplifiers [8–10], for improved energy efficiency. However, these works primarily address static power consumption, while noise performance remains inherently constrained by the gm-and-C imposed limit. This paper introduces a novel noise-reducing Stacked Dynamic Source-Follower Amplifier (Stacked DySFA). The proposed structure dynamically achieves gain, while matched and stacked source followers (SFs) exhibit current reuse and capacitance extension effects, which jointly contribute to reducing the overall noise and energy. Additionally, benefiting from the inherent linearity of an SF-based amplifier, this paper presents a proof-of-concept high-resolution five-stage pipelined SAR ADC achieving 12.7-bit ENOB and 176 dB Schreier FoM under a 1.8 V supply in 180 nm CMOS.