Editorial: Smart dust: Micro and nano scale devices for highly-integrated localized and distributed smart systems for precision and personalized medicine

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As big strides were being made in many science fields in the 1970s and 80s, faster computation for solving problems in molecular biology, semiconductor technology, aeronautics, particle physics, etc., was at the forefront of research. Parallel and super-co ...

Positron emission tomography is a nuclear imaging technique well known for its use in oncology for cancer diagnosis and staging. A PET scanner is a complex machine which comprises photodetectors placed in a ring configuration that detect gamma photons gen ...

With the proliferation of ultrahigh-speed mobile networks and internet-connected devices, along with the rise of artificial intelligence (AI)(1), the world is generating exponentially increasing amounts of data that need to be processed in a fast and effic ...

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabr ...

This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2 K to ...

We will present and discuss some of the great research challenges and opportunities related to 21st century energy efficient computing and sensing devices and systems, in the context of the Internet of Things (IoT) revolution. In the future, major innovati ...

The vast majority of disruptive innovations in science and technology has been originated from the discovery of a new material or the way its properties have been exploited to create novel devices and systems. New advanced nanomaterials will have a lasting ...

With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main drive ...

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

High pressure-rated channels allow microfluidic assays to be performed on a smaller footprint while keeping the throughput, thanks to the higher enabled flow rates, opening perspectives for cost-effective integration of CMOS chips to microfluidics circuits ...

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single ...

A multiphonon-assisted model included in a Poisson-Schroedinger solver has been applied to the calculation of the capture/emission trapping rates of CMOS oxide interface defects. The dependencies of trap capture cross-sections with trap energy, depth, appl ...

The electronics industry is present nowadays in the most various applications. A new type of technology for integrated circuits named BCD has started to be developed and appeared from the mid 1980’s. This new technology allows integrating bipolar transisto ...

The influence of the geometry, via the ratio L/W of the Hall cells and the geometrical correction factor G on several figures of merit regarding Hall sensors is analyzed, namely the sensitivity, Hall Voltage and power dissipated within the device. Experime ...

In this paper, the impact of the wire grid size on the power-delay-area trade off of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complet ...

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based ...

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. ...

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted si ...

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 μm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ...

The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is ...

Editorial: Smart dust: Micro and nano scale devices for highly-integrated localized and distributed smart systems for precision and personalized medicine

Chattez avec Graph Search

Nano-MOSFET - Foundation of Quantum Computing Part I

Integrated electronics for time-of-flight positron emission tomography photodetectors

Parallel convolutional processing using an integrated photonic tensor core

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Voltage References for the Ultra-Wide Temperature Range from 4.2 K to 300 K in 40-nm CMOS

The Future of Electronics: Silicon to Cloud Technologies

Reconfigurable electronics based on metal-insulator transition : steep-slope switches and high frequency functions enabled by Vanadium Dioxide

Design Methodologies and CAD for Emerging Nanotechnologies

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Parylene to silicon nitride bonding for post-integration of high pressure microfluidics to CMOS devices

K-band single-chip electron spin resonance detector

Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model

Substrate Current Modeling for high Temperature Smart Power BCD Technology

Geometry influence on the Hall effect devices performance

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS

Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits