High-Precision Performance Estimation of Dynamic Dataflow Programs

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High-Precision Performance Estimation of Dynamic Dataflow Programs

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Highly Parallel RTL Simulation

Oligolithic Cross-task Optimizations across Isolated Workloads

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

Chaosity: Understanding Contemporary NUMA-architectures

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

Acceleration of graph pattern mining and applications to financial crime

Post-Moore's Law Fusion: High-Bandwidth Memory, Accelerators, and Native Half-Precision Processing for CPU-Local Analytics

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Imprecise Store Exceptions

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers