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Imaging sensor device using an array of single-photon avalanche diode photodetectors

The invention relates to an Imaging sensor device in a stacked arrangement comprising: - a pixel array tier comprising a plurality of pixel segments each having a plurality of pixels for photon detection each providing a digital pixel output; - a processin ...

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Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

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Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

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EPFL2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

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Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

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Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

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ACM2023

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ACM2023

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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

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STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale

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FRONTIERS MEDIA SA2022

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Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022