Publications associées à A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Mirjana Stojilovic, Wei Hu, Dina Gamaleldin Ahmed Shawky Mahmoud, Beatrice Shokry Samir Shokry

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

2024

Technology-Aware Logic Synthesis for Superconducting Electronics

Giovanni De Micheli, Dewmini Sudara Marakkalage, Siang-Yun Lee, Alessandro Tempia Calvino, Mingfei Yu, Rassul Bairamkulov

Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. Today, the lack of tools for the design of large-scale integrated superconducting circuits is a major obst ...

2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Ognjen Glamocanin

The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...

EPFL2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Ognjen Glamocanin, Dina Gamaleldin Ahmed Shawky Mahmoud

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

Optimizing Quantum Compilers: Efficient and Effective Algorithms

Fereshte Mozafari Ghoraba

Quantum computing has made significant progress in recent years, with Google and IBM releasing quantum computers with 72 and 50 qubits, respectively. Google has also achieved quantum supremacy with its 54-qubit device, and IBM has announced the release of ...

EPFL2023

Chaosity: Understanding Contemporary NUMA-architectures

Anastasia Ailamaki, Viktor Sanca, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Andreea Nica

Modern hardware is increasingly complex, requiring increasing effort to understand in order to carefully engineer systems for optimal performance and effective utilization. Moreover, established design principles and assumptions are not portable to modern ...

2023

ROSMOSE: A Web-based Optimization Tool to Aid Decision-making for the Design and Operation of Industrial and Urban Energy Systems

François Maréchal, Cédric Terrier, Daniel Alexander Florez Orrego, Michel Lopez, Meire Ellen Gorete Ribeiro Domingos

Energy efficiency is crucial for the sustainable operation of all industrial and urban sectors. However, practicing engineers have seldom access to open-source tools that can readily evaluate and compare scenarios in terms of energy consumption, cost, and ...

2023

Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems

David Atienza Alonso, Benoît Walter Denkinger, Miguel Peon Quiros

Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...

2023

Artificial Neural Network Training on an Optical Processor via Direct Feedback Alignment

Florent Gérard Krzakala, Julien Marcel Daniel Emmanuel Launay

Artificial Neural Networks (ANN) are habitually trained via the back-propagation (BP) algorithm. This approach has been extremely successful: Current models like GPT-3 have O(10 11 ) parameters, are trained on O(10 11 ) words and produce awe-inspiring resu ...

IEEE2023

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Giovanni De Micheli, Heinz Riener, Alessandro Tempia Calvino, Shubham Rai, Akash Kumar

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, David Dervishi, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations

Alexandre Schmid, Lizeth Gonzalez Carabarin

Model compression techniques have lead to a reduction of size and number of computations of Deep Learning models. However, techniques such as pruning mostly lack of a real co-optimization with hardware platforms. For instance, implementing unstructured pru ...

IEEE2022

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Andres Upegui, Francesco Regazzoni, Andrea Guerrieri

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022