Alessandro Tempia Calvino

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Logic synthesis is a key component of electronic design automation (EDA) tools, essential for designing high-performance, compact, and power-efficient integrated circuits. The continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technol ...

Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconducting elec ...

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

We address the problem of minimizing the area of circuits mapped to a technology library, with or without delay constraints. While traditional methods optimize first a technology-independent representation and then perform technology mapping to a library, ...

Rapid single-flux quantum (RSFQ) is one of the most advanced superconducting technologies with the potential to supplement or replace conventional VLSI systems. However, scaling RSFQ systems up to VLSI complexity is challenging due to fundamental differenc ...

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Before physical design can be performed, AQFP technology mapping involves not only mapping logic into supported gate types but also legalizing the circuit to fulfil ...

The Adiabatic Quantum-Flux Parametron (AQFP) is an energy-efficient superconducting logic family. AQFP technology requires buffer and splitting elements (B/S) to be inserted to satisfy path-balancing and fanout-branching constraints. B/S insertion policies ...

Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. Today, the lack of tools for the design of large-scale integrated superconducting circuits is a major obst ...

Quantum oracle synthesis involves compiling arbitrary Boolean functions into quantum circuits using specific quantum gates supported by the target quantum computer. The Clifford+T gate library is particularly common in fault-tolerant quantum computing syst ...

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

Factored form is a powerful multi-level representa- tion of a Boolean function that readily translates into an imple- mentation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number ...

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive comp ...

This paper addresses the challenge of reducing the number of nodes in Look-Up Table (LUT) networks with two significant applications. First, Field-Programmable Gate Arrays (FPGAs) can be modelled as networks of LUTs, and minimizing the node count is impera ...

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

The rapid growth of cloud computing has intensified the need for secure data outsourcing solutions. Fully homomorphic encryption (FHE) offers a promising approach by enabling computations on encrypted data without exposing the plaintext. This paper advance ...

Model-checking intends to verify whether a property is satisfied by a model, or not. Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present papers proposes a ne ...

The majority-inverter graph (MIG) is a homogeneous logic network widely used in logic synthesis for majority-based emerging technologies. Many logic optimization algorithms have been proposed for MIGs, including rewriting, resubstitution, and graph mapping ...

This paper proposes a versatile mapping approach that has three objectives: i) it can map from one technology-independent graph representation to another; ii) it can map to a cell library; iii) it supports logic rewriting. The method is cut-based, mitigate ...

Alessandro Tempia Calvino

Chattez avec Graph Search

Technology Mapping and Optimization Algorithms for Logic Synthesis of Advanced Technologies

Majority-based Design Flow for AQFP Superconducting Family

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Technology Mapping Using Multi-output Library Cells

Area-Oriented Optimization After Standard-Cell Mapping

Synthesis of SFQ Circuits with Compound Gates

Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron

Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits

Technology-Aware Logic Synthesis for Superconducting Electronics

Back-end-aware Fault-tolerant Quantum Oracle Synthesis

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Improving Standard-Cell Design Flow using Factored Form Optimization

Enhancing Delay-Driven LUT Mapping with Boolean Decomposition

Area-Oriented Resubstitution For Networks of Look-Up Tables

Scalable Logic Rewriting Using Don’t Cares

On the Synthesis of High-performance Homomorphic Boolean Circuits

Direct Model-checking of SysML Models

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

A Versatile Mapping Approach for Technology Mapping and Graph Optimization

Boolean Decomposition Revisited