Publications de Ali Saeidi | EPFL Graph Search

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The present invention relates to a semiconductor sensor (1) comprising: a source element (17, 19); a drain element (21, 23); a semiconductor channel element (25) between the source element (17, 19) and the drain element (21, 23) for forming an electrically ...

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applicati ...

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a ...

We report the first experimental demonstration and performance characterization of a fully integrated negative capacitance (NC) WSe2/SnSe2 p-type Tunnel FETs (TFETs), validating the use of NC as a technology booster to achieve a significantly improved sub- ...

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for th ...

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capac ...

In this paper, we experimentally explore the transient negative capacitance effect in ferroelectric high-k gate stacks using multi-ferroelectric domain Si-doped HfO2 with and without the metal plane, MFMIS (TiN/Si:HfO2/TiN/SiO2) and MFIS (TiN/Si:HfO2/SiO2) ...

The co-integration of logic switches and neuromorphic functions could be used to create new computing architectures with low power consumption and novel functionalities. Two-dimensional (2D) semiconductors and ferroelectric materials could be potentially u ...

We report the universal boosting impact of a true negative capacitance (NC) effect on digital and analog performances of Tunnel FETs (TFETs), mirrored for the first time in near hysteresis-free experiments and exploiting the S-shaped polarization character ...

Impact of physical parameters of ferroelectric layer on the performance of Negative Capacitance (NC) MOSFETs is experimentally studied in this paper. Electrical behaviors of PZT-based and Si:HfO2-based NC-FETs are investigated and discussed. In a PZT-based ...

In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the f ...

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

This experimental study investigates a novel multi-functional one dimensional-two dimensional (1D-2D) heterojunction made of two different band-gap semiconductors, i.e. single-walled carbon nanotube (SWCNT) and tungsten di-selenide (WSe2). The proposed ult ...

This correspondence highlights that the Gibbs free energy description of a ferroelectric capacitor in series with a paraelectric capacitor, depends on the initial charge on the plates of the ferroelectric capacitor. An incomplete Gibbs free energy descript ...

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a ...

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond- ...

This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative ca ...

Ali Saeidi

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Negative capacitance semiconductor sensor

Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

Fully integrated Si:HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETs

Subthermionic negative capacitance ion sensitive field-effect transistor

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Exploration of Negative Capacitance Devices and Technologies

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Transient Negative Capacitance of Silicon-doped HfO2 in MFMIS and MFIS structures: experimental insights for hysteresis-free steep slope NC FETs

Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices

Near Hysteresis-Free Negative Capacitance InGaAs Tunnel FETs with Enhanced Digital and Analog Figures of Merit below VDD=400mV

Design Considerations of Ferroelectric Properties for Negative Capacitance MOSFETs

An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays: Digital and Analog Figures of Merit from 300K to 10K

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction

Corrections to “Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization”

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer

Negative Capacitance Field Effect Transistors; Capacitance Matching and non-Hysteretic Operation