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The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for ...

While research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support has not emerged so far, and thus the creation of such systems remains a difficult, time-consuming and error-prone pr ...

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for comp ...

This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are th ...

This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signa ...

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

The analysis of the trace graphs generated by dataflow program executions has been shown to be an effective tool for exploring and optimizing the design space of application programs on manycore/multicore platforms. In this work a new approach aiming at fi ...

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

This paper presents shared-variable synchronization approaches for dataflow programming. The mechanisms do not require any substantial model of computation (MoC) modification, and is portable across both for hardware (HW) and software (SW) low-level code s ...

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity fo ...

One of the problems proven to be NP-hard in the field of many-core architectures is the partitioning of stream programs. In order to maximize the execution parallelism and obtain the maximal data throughput for a streaming application it is essential to fi ...

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application co ...

This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow desc ...

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementat ...

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synt ...

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Endri Bezati

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High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework

High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Generating hardware and software for RISC-V cores generated with Rocket Chip generator

Methods to explore design space for MPEG RMC codec specifications

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Synthesis and optimization of high-level stream programs

MPEG high efficient video coding stream programming and many-cores scalability

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms