Andreas Peter Burg

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Publications associées (211)

MIMO transmission with residual transmit-RF impairments

Christoph Studer, Andreas Peter Burg

IEEE2010

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Pascal Andreas Meinerzhagen, Christoph Studer, Andreas Peter Burg

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and ...

IEEE2010

Matching pursuit: Evaluation and implementatio for LTE channel estimation

Andreas Peter Burg

IEEE2010

Simulation and Emulation of MIMO Wireless Baseband Transceivers

Andreas Peter Burg

The development of state-of-the-art wireless communication transceivers in semiconductor technology is a challenging process due to complexity and stringent requirements of modern communication standards such as IEEE 802.11n. This tutorial paper describes ...

2010

Low-complexity Seysen's algorithm based lattice reduction-aided MIMO detection for hardware implementations

Andreas Peter Burg, Carl Christian Sten Dominic Senning

IEEE2010

Area- and throughput-optimized VLSI architecture of sphere decoding

Christoph Studer, Andreas Peter Burg

IEEE2010

The effect of unreliable LLR storage on the performance of MIMO-BICM

Christoph Studer, Andreas Peter Burg

IEEE2010

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

Andreas Peter Burg, Carl Christian Sten Dominic Senning

An IEEE 802.11n baseband transceiver ASIC is implemented in 0.13 mu m CMOS technology. The implementation has a core area of 14.4 mm(2) and is the first to support the optional 3- and 4-stream MIMO transmission modes of the standard for data rates up to 60 ...

Ieee Service Center Single Publication Sales Unit, 445 Hoes Lane, Piscataway, Nj 08854 Usa2009

Design and Optimization of an HSDPA Turbo Decoder ASIC

Qiuting Huang, Andreas Peter Burg

Institute of Electrical and Electronics Engineers2009

A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization

Andreas Peter Burg

When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MI ...

2008

A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS

Qiuting Huang, Andreas Peter Burg

This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s requ ...

2008

Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

Christoph Studer, Andreas Peter Burg, Nicholas Alexander Preyss

We describe a fully reconfigurable low-density parity check (LDPC) decoder for quasi-cyclic (QC) codes. The proposed hardware architecture is able to decode virtually any QC-LDPC code that fits into the allocated memories while achieving high decoding thro ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Soft-output sphere decoding: Algorithms and VLSI implementation

Christoph Studer, Andreas Peter Burg

Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high computational complexity. In this paper, we show how sphere decoding can be ...

2008

FFT processor for OFDM channel estimation

Andreas Peter Burg

Pilot-assisted channel estimation for communication systems employing orthogonal frequency division multiplexing modulation requires significant signal processing at the receiver if the correlation among the frequency-domain channel coefficients is to be e ...