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Vasileios Pavlidis

Cette personne a quitté l’EPFL

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Publications associées (21)

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An Enhanced Design Methodology for Resonant Clock Trees

Giovanni De Micheli, Vasileios Pavlidis, Xifan Tang, Somayyeh Rahimian Omam

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

American Scientific Publishers2013

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

2012

Low-power clock distribution networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

2012

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Springer-Verlag2011

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Hu Xu, Wayne Burleson

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012

Analytical Heat Transfer Model for Thermal Through-Silicon Vias

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on th ...

2011

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010

Inter-Plane Communication Methods for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Three-dimensional (3-D) integration is an emerging candidate for implementing high performance multifunctional systems-on-chip. Employing an efficient medium for data communication among different planes is a key factor in achieving a high performance 3-D ...

American Scientific Publishers2012

Physical Design Issues in 3-D Integrated Technologies

Vasileios Pavlidis

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dime ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Design Methods and Tools for 3D Integration

Giovanni De Micheli, Yusuf Leblebici, David Atienza Alonso, Vasileios Pavlidis

The design of 3-dimensional integrated circuits requires new specialized tools, methods and flows. Whereas some tools are on the market and some design flows for standard ICs are extended to handle die stacking and through-silicon vias, much R&D has still ...

2011

Clock Distribution Networks in 3-D Integrated Systems

Vasileios Pavlidis

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock di ...

2011

Synchronization and Power Integrity Issues in 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Several challenges should be resolved for three dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3 ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

A Novel Framework for Exploring 3-D FPGAs with Heterogeneous Interconnect Fabric

Vasileios Pavlidis

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the pr ...

2012

Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Power Distribution Paths for 3-D IC

Giovanni De Micheli, Vasileios Pavlidis

Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) cir ...

ACM Order Department, P.O. Box 64145, Baltimore, MD 21264 USA2009

Clock and Power Distribution Networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis

Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal ...

2009

3.5-D Integration: A Case Study

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Ciprian Seiculescu, Vasileios Pavlidis, Shashi Kanth Bobba

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

2009