Simulateur logiqueLogic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate level, register-transfer level (RTL), electronic system-level (ESL), or behavioral level. Logic simulation may be used as part of the verification process in designing hardware. Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design.
Simulation informatiquevignette|upright=1|Une simulation informatique, sur une étendue de , de l'évolution du typhon Mawar produite par le Modèle météorologique Weather Research and Forecasting La simulation informatique ou numérique est l'exécution d'un programme informatique sur un ordinateur ou réseau en vue de simuler un phénomène physique réel et complexe (par exemple : chute d’un corps sur un support mou, résistance d’une plateforme pétrolière à la houle, fatigue d’un matériau sous sollicitation vibratoire, usure d’un roulem
Simulation de phénomènesLa simulation de phénomènes est un outil utilisé dans le domaine de la recherche et du développement. Elle permet d'étudier les réactions d'un système à différentes contraintes pour en déduire les résultats recherchés en se passant d'expérimentation. Les systèmes technologiques (infrastructures, véhicules, réseaux de communication, de transport ou d'énergie) sont soumis à différentes contraintes et actions. Le moyen le plus simple d'étudier leurs réactions serait d'expérimenter, c'est-à-dire d'exercer l'action souhaitée sur l'élément en cause pour observer ou mesurer le résultat.
Optimizing compilerIn computing, an optimizing compiler is a compiler that tries to minimize or maximize some attributes of an executable computer program. Common requirements are to minimize a program's execution time, memory footprint, storage size, and power consumption (the last three being popular for portable computers). Compiler optimization is generally implemented using a sequence of optimizing transformations, algorithms which take a program and transform it to produce a semantically equivalent output program that uses fewer resources or executes faster.
Transaction-level modelingTransaction-level modeling (TLM) is an approach to modelling complex digital systems by using electronic design automation software. TLM language (TLML) is a hardware description language, usually, written in C++ and based on SystemC library. TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.
High-level synthesisHigh-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as clock-level timing.
Langage de programmation de haut niveauEn programmation informatique, un langage de programmation à haut niveau d'abstraction généralement appelé langage de haut niveau est un langage de programmation orienté autour du problème à résoudre, qui permet d'écrire des programmes en utilisant des mots usuels des langues naturelles (très souvent de l'anglais) et des symboles mathématiques familiers. Un langage de haut niveau fait abstraction des caractéristiques techniques du matériel utilisé pour exécuter le programme, tels que les registres et les drapeaux du processeur.
Electronic system-level design and verificationElectronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, an EDA-industry-analysis firm, on February 1, 2001. It is defined in ESL Design and Verification as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner.
Conception assistée par ordinateur pour l'électroniqueLa CAO électronique (pour Conception assistée par ordinateur électronique), nommée également en anglais EDA (pour Electronic design automation), est la catégorie des outils servant à la conception et la production des systèmes électroniques allant des circuits imprimés jusqu'aux circuits intégrés. Le terme CAO est aussi utilisé pour désigner la CAO mécanique, la conception assistée par ordinateur et la fabrication assistée par ordinateur en électronique et en électrotechnique.
Analyse temporelle statiqueL’analyse temporelle statique (en anglais : static timing analysis, TSA) est une méthode d'évaluation de la fréquence de fonctionnement d'un circuit intégré. Contrairement à l'analyse dynamique, elle ne nécessite pas l'usage de vecteur de test ni de simulation. Elle repose sur le calcul et l'addition des délais de chaque porte logique élémentaire d'un circuit. L'analyse temporelle statique permet de calculer le plus long chemin logique d'un circuit, le chemin critique.
Stochastic simulationA stochastic simulation is a simulation of a system that has variables that can change stochastically (randomly) with individual probabilities. Realizations of these random variables are generated and inserted into a model of the system. Outputs of the model are recorded, and then the process is repeated with a new set of random values. These steps are repeated until a sufficient amount of data is gathered. In the end, the distribution of the outputs shows the most probable estimates as well as a frame of expectations regarding what ranges of values the variables are more or less likely to fall in.
Logic optimizationLogic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design. Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.
Vérification formelleIn the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics. Formal verification can be helpful in proving the correctness of systems such as: cryptographic protocols, combinational circuits, digital circuits with internal memory, and software expressed as source code.
Simulation softwareSimulation software is based on the process of modeling a real phenomenon with a set of mathematical formulas. It is, essentially, a program that allows the user to observe an operation through simulation without actually performing that operation. Simulation software is used widely to design equipment so that the final product will be as close to design specs as possible without expensive in process modification. Simulation software with real-time response is often used in gaming, but it also has important industrial applications.
Signoff (electronic design automation)In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that the design must pass before it can be taped out. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: front-end sign-off and back-end sign-off. After back-end sign-off, the chip goes to fabrication.
Synthèse logiqueEn électronique, la synthèse logique (RTL synthesis) est la traduction d'une forme abstraite de description du comportement d'un circuit (voir Register Transfer Level) en sa réalisation concrète sous forme de portes logiques. Le point de départ peut être un langage de description de matériel comme VHDL ou Verilog, un schéma logique du circuit. D'autres sources sont venues s'additionner depuis les années 2010, comme l'utilisation de la programmation en OpenCL. Le point d'arrivée peut être un code objet pour un CPLD ou FPGA ou la création d'un ASIC.
Intelligent verificationIntelligent Verification, including intelligent testbench automation, is a form of functional verification of electronic hardware designs used to verify that a design conforms to specification before device fabrication. Intelligent verification uses information derived from the design and specification(s) to expose bugs in and between hardware IPs. Intelligent verification tools require considerably less engineering effort and user guidance to achieve verification results that meet or exceed the standard approach of writing a testbench program.
Register Transfer LevelRegister Transfer Level (RTL) est une méthode de description des architectures microélectroniques. Dans la conception RTL, le comportement d'un circuit est défini en termes d'envois de signaux ou de transferts de données entre registres, et les opérations logiques effectuées sur ces signaux. Le RTL est utilisé dans les langages de description matérielle (HDL) comme Verilog et VHDL pour créer des représentations d'un circuit à haut niveau, à partir duquel les représentations à plus bas niveau et le câblage réel peuvent être dérivés.
Standard cellIn semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect.
Continuous simulationContinuous Simulation refers to simulation approaches where a system is modeled with the help of variables that change continuously according to a set of differential equations. It is notable as one of the first uses ever put to computers, dating back to the Eniac in 1946. Continuous simulation allows prediction of rocket trajectories hydrogen bomb dynamics (N.B. this is the first use ever put to the Eniac) electric circuit simulation robotics Established in 1952, the Society for Modeling and Simulation International (SCS) is a nonprofit, volunteer-driven corporation dedicated to advancing the use of modeling & simulation to solve real-world problems.
