Cours

CS-470: Advanced computer architecture

Résumé

This course explores techniques for exploiting instruction-level parallelism both statically and dynamically. It also addresses the generation of hardware accelerators from programming languages and investigates security issues related to microarchitectural features, including side-channel attacks.

Séances de cours

Enseignant·e

Paolo Ienne

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.

Source officielle

Page Moodle

http://go.epfl.ch/CS-470

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Résumé

Séances de cours

Enseignant·e

Paolo Ienne

Source officielle

Page Moodle

http://go.epfl.ch/CS-470

Séances de ce cours (14)

Pipelining: Amélioration des performances de l'architecture informatique

Couvre la pipelining dans l'architecture informatique, en mettant l'accent sur son rôle dans l'amélioration des performances grâce à un parallélisme au niveau de l'instruction et en abordant les défis associés.

Planification dynamique dans les processeurs : amélioration de l'exécution des instructions

Couvre la planification dynamique dans les processeurs, en se concentrant sur l'exécution dans le désordre et la gestion efficace des dépendances d'instructions.

Renommer : Techniques et architectures

Couvre les techniques de renommage des registres essentielles pour éliminer les risques d'exécution dans les processeurs modernes.

Prédiction et spéculation dans la conception du processeur

Couvre les techniques de prédiction et de spéculation dans la conception du processeur pour améliorer les performances et réduire les retards d'exécution.

Comprendre le multithreading simultané dans les processeurs modernes

Couvre le multithreading simultané, sa mise en œuvre et son impact sur les performances du processeur.

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