Shashwat ShrivastavaI am a Ph.D. student at EPFL, advised by Dr. Mirjana Stojilović. I am broadly interested in FPGA architecture and Computer-Aided Design. My research is focused on reducing the compile time for FPGAs by incorporating architectural enhancements and rethinking CAD algorithms.
Michel SchinzEnseignement et PhD Cours Advanced compiler construction CS-420 Les étudiants apprennent plusieurs techniques de mise en œuvre des langages fonctionnels et orienté-objets. Ils les mettent en pratique en réalisant certaines parties importantes d'un compilateur et d'un moteur d'exécution pour un langage fonctionnel simple. Pratique de la programmation orientée-objet CS-108 Les étudiants perfectionnent leurs connaissances en Java et les mettent en pratique en réalisant un projet
Christoph KochEnseignement et PhD Doctorant·es actuel·les Léonard Léchot, Zhekai Jiang, Hanbit Lee A dirigé les thèses EPFL de Immanuel Trummer, Aleksandar Vitorovic, Milos Nikolic, Daniel Lupei, Mohammed El Seidy, Ioannis Klonatos, Mohammad Dashti Rahmat Abadi, Amir Shaikhha, Lionel Parreaux, Sachin Basil John, Zilu Tian A co-dirigé les thèses EPFL de David Kozhaya Cours Making intelligent things A CS-358(a) Le cours vise à enseigner le prototypage d'artefacts physiques intelligents et à résoudre des d
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Giovanni De MicheliExpertise
Technologies de conception pour les systèmes intégrés, tels que la synthèse, le codesign de HW/SW et la conception de basse puissance. Technologies de conception des systèmes sur les plateformes hétérogènes comprenant les composants électriques, et biologiques.
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Enseignement et PhD A dirigé les thèses EPFL de Abhishek Garg, Mohamed Haykel Ben Jamaa, Francesco Zanini, Ciprian Seiculescu, Cristina Boero, Hu Xu, Andrea Cavallini, Shashi Kanth David Atienza AlonsoDavid Atienza Alonso is an associate professor of EE and director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) servers and edge AI architectures. Dr. Atienza has co-authored more than 350 papers, one book, and 12 patents in these previous areas. He has also received several recognitions and award, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned two best paper awards at the VLSI-SoC 2009 and CST-HPCS 2012 conference, and five best paper award nominations at the DAC 2013, DATE 2013, WEHA-HPCS 2010, ICCAD 2006, and DAC 2004 conferences. He serves or has served as associate editor of IEEE Trans. on Computers (TC), IEEE Design & Test of Computers (D&T), IEEE Trans. on CAD (T-CAD), IEEE Transactions on Sustainable Computing (T-SUSC), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019 and was GOLD member of the Board of Governors of IEEE CASS from 2010 to 2012. He is a Distinguished Member of ACM and an IEEE Fellow.
Martin OderskyEnseignement et PhD Doctorant·es actuel·les Matthieu Bovel, Yaoyu Zhao, Anna Herlihy, Nguyên Cao Pham, Yichen Xu A dirigé les thèses EPFL de Julie Vachon, Matthias Zenger, Michel Schinz, Philippe Altherr, Vincent Cremet, Burak Emir, Stéphane Micheloud, Iulian Dragos, Philipp Haller, Gilles Dubochet, Tiark Rompf, Ingo Maier, Lukas Rytz, Aleksandar Prokopec, Heather Miller, Vlad Ureche, Nada Amin, Manohar Jonnalagedda, Hubert Plociniczak, Vojin Jovanovic, Sandro Stucki, Eugene Burmako, Dmytro Petrashko, Séb