Publications associées à Flow to HDL

Publications associées (10)

High level synthesis of Smith-Waterman dataflow implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by wr ...

2017

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application co ...

Springer Verlag2015

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Jian Zhang, Subhasish Mitra

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

Assoc Computing Machinery2014

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Springer Heidelberg2014

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Yusuf Leblebici, Vladan Popovic, Eliéva Arlette Pignat

This brief analyzes the performance of the hardware-based tone mapping operators for compression of high dynamic range images. The bottlenecks of a tone mapping system are determined and a high-performance field programmable gate array (FPGA) implementatio ...

Institute of Electrical and Electronics Engineers2014

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Paolo Ienne, Andreas Peter Burg, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna, Gabriel Falcao Paiva Fernandes

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

Supporting Dimensional Analysis in SystemC-AMS

Alain Vachoux, Torsten Mähne

This paper will introduce new modeling capabilities for SystemC-AMS to describe energy conserving multi-domain systems in a formal and consistent way at a high level of abstraction. To this end, all variables and parameters of the system model need to be a ...

IEEE2009

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

Marco Mattavelli, Richard Thavot, Romuald Mosqueron

This paper presents a contribution to the development of rapid prototyping tools based on data-flow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cas ...

2009

Development of a Bond Graph Based Model of Computation for SystemC-AMS

Yusuf Leblebici, Alain Vachoux, Torsten Mähne

The modelling and simulation capabilities of SystemC-AMS concerning conservative continuous time systems involving the interaction of several physical domains and with digital control components are currently limited. Bond graphs unify the description of m ...

2008

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006