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Concept

Microprocesseur à jeu d'instruction étendu

Publications associées (27)

Fast Block Sequential Decoding of Polar Codes

Kirill Ivanov

A reduced complexity sequential decoding algorithm for polar (sub) codes is described. The proposed approach relies on a decomposition of the polar (sub) code being decoded into a number of outer codes, and on-demand construction of codewords of these code ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Boolean satisfiability in quantum compilation

Giovanni De Micheli, Mathias Soeken, Heinz Riener, Bruno Schmitt Antunes, Giulia Meuli, Fereshte Mozafari Ghoraba

Quantum compilation is the task of translating a quantum algorithm implemented in a high-level quantum programming language into a technology-dependent instructions flow for a physical quantum computer. To tackle the large gap between the quantum program a ...

ROYAL SOC2020

Malware in the SGX supply chain: Be careful when signing enclaves!

Rafael Pereira Pires

Malware attacks are a significant part of the new software security threats detected each year. Intel Software Guard Extensions (SGX) are a set of hardware instructions introduced by Intel in their recent lines of processors that are intended to provide a ...

2022

Modifying Stride Length in Isolation and in Combination With Foot Progression Angle and Step Width Can Improve Knee Kinetics Related to Osteoarthritis; A Preliminary Study in Healthy Subjects

Brigitte Jolles-Haeberli

The purpose of this study was to determine the effects of modifying stride length (SL) on knee adduction and flexion moments, two markers of knee loading associated with medial-compartment knee osteoarthritis (OA) progression. This study also tested if SL ...

2020

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019