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Concept

Instruction unit

Publications associées (17)

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Biosensors for Bimolecular Computing: a Review and Future Perspectives

Sandro Carrara, Danilo Demarchi, Simone Aiassa

Biomolecular computing is the field of engineering where computation, storage, communication, and coding are obtained by exploiting interactions between biomolecules, especially DNA, RNA, and enzymes. They are a promising solution in a long-term vision, br ...

SPRINGER2020

Prefetched Address Translation

Edouard Bugnion, Boris Robert Grot, Dmitrii Ustiugov

With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a ...

ASSOC COMPUTING MACHINERY2019

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Willy Zwaenepoel, Andrzej Pawel Nowak

Dynamic instruction mixes form an important part of the toolkits of performance tuners, compiler writers, and CPU architects. Instruction mixes are traditionally generated using software instrumentation, an accurate yet slow method, that is normally limite ...

2018

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

Paolo Ienne, Atri Bhattacharyya

Dynamically-scheduled elastic circuits generated by High-Level Synthesis (HLS) tools are inherently out-of-order, following the flow of data rather than the evolution of an instruction pointer. Components of the circuit which access memory need to be conne ...

2018

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Simulation of High-Performance Memory Allocators

David Atienza Alonso

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Ahmed Yasir Dogan

Springer-Verlag Heidelberg2011

Recent Developments in Flow Boiling and Two-Phase Flow in Small Channels and Microchannels

John Richard Thome, Andrea Cioncolini

Microscale two-phase flow is at present one of the hottest topics of heat transfer research, both in academia and in the industry. The miniaturization of two-phase flow systems, which has led to numerous experimental and theoretical challenges not yet comp ...

Taylor & Francis2010

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004